Deliverables
2nd 18 month period report
Specification for visible image sensor (supply voltage, noise, hot carrier injection, reliability specifications) Cost evaluation of the low cost version of FDSOI dedicated for the analog layer and comparison with the standard BULK technology
Deep analysis of low temperature analog MOSFET, conclusions on the process performance adequation with ST specifications
1st 18 month period report
A project web-page will be established and a system will be worked out to allow partners to edit and contribute to the cite. The structure will be finished by m6 but the content will be edited throughout the project live time.
Delivery of the bottom strata composed of FDSOI technology MOSFET and 4 metal line levels
The purpose of the data management plan (DMP) is to define the main elements of the data management policy that will be used by the 3D-MUSE consortium partners with regard to all the datasets that will be generated within the project. As part of the dissemination and exploitation activities, the 3D-MUSE DMP will be drafted and updated during the execution of the project, i.e., it is not a fixed document, but evolves during the lifespan of the project. Updates will be reported with the periodic project reports. In accordance with the H2020 guideline, the 3D-MUSE DMP outlines how research data will be handled during project execution, and after its completion, i.e., post-project, essentially along the lines of exploitation and commercialisation.
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Publications
Author(s): F. Andrieu, P. Batude, L. Brunet, C. Fenouillet-Beranger, D. Lattard, S. Thuries, O. Billoint, R. Fournel, M. Vinet
Published in: 2018 International Conference on IC Design & Technology (ICICDT), 2018, Page(s) 141-144
DOI: 10.1109/icicdt.2018.8399776
Author(s): L. Brunet, C. Fenouillet-Beranger, P. Batude, S. Beaurepaire, F. Ponthenier, N. Rambal, V. Mazzocchi, J-B. Pin, P. Acosta-Alba, S. Kerdiles, P. Besson, H. Fontaine, T. Lardin, F. Fournel, V. Larrey, F. Mazen, V. Balan, C. Morales, C. Guerin, V. Jousseaume, X. Federspiel, D. Ney, X. Garros, A. Roman, D. Scevola, P. Perreau, F. Kouemeni-Tchouake, L. Arnaud, C. Scibetta, S. Chevalliez, F. Aussenac, J
Published in: 2018 IEEE International Electron Devices Meeting (IEDM), 2018, Page(s) 7.2.1-7.2.4
DOI: 10.1109/iedm.2018.8614653
Author(s): P. Batude, L. Brunet, C. Fenouillet-Beranger, F. Andrieu, J.-P. Colinge, D. Lattard, E. Vianello, S. Thuries, O. Billoint, P. Vivet, C. Santos, B. Mathieu, B. Sklenard, C.-M. V. Lu, J. Micout, F. Deprat, E. Avelar Mercado, F. Ponthenier, N. Rambal, M.-P. Samson, M. Casse, S. Hentz, J. Arcamone, G. Sicard, L. Hutin, L. Pasini, A. Ayres, O. Rozeau, R. Berthelon, F. Nemouchi, P. Rodriguez, J.-B. Pin,
Published in: 2017 IEEE International Electron Devices Meeting (IEDM), 2017, Page(s) 3.1.1-3.1.4
DOI: 10.1109/iedm.2017.8268316
Author(s): Pascal Vivet, Sebastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigne, Perrine Batude
Published in: 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, Page(s) 157-160
DOI: 10.1109/icecs.2018.8617955
Author(s): Pascal Vivet, Gilles Sicard, Laurent Millet, Stephane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sebastien Thuries, Didier Lattard, Cheramy Severine, Perrine Batude, Fabien Clermidy
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 674-679
DOI: 10.23919/date.2019.8714886
Author(s): S. Cheramy, A. Jouve, C. Fenouillet-Beranger, P. Batude, M. Vinet
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, Page(s) 1-5
DOI: 10.1109/s3s.2018.8640158
Author(s): Laurent Brunet, Perrine Batude, Claire Fenouillet-Beranger, Maud Vinet
Published in: ECS Transactions, Issue 85/8, 2018, Page(s) 125-130, ISSN 1938-5862
DOI: 10.1149/08508.0125ecst