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Low Energy Toolset for Heterogeneous Computing

Deliverables

Report on evaluation of efficiency and TCO improvements of use-cases

The evaluations of efficiency and TCO improvements of the three use-cases and the secure IoT gateway will be described, based on the metrics defined in T5.1. T5.1, T5.6

First release of the task-based runtime

First detailed report on the heterogeneous, energy-efficient, secure & resilient task-based runtime

Project Management and Quality Guidelines

This deliverable will describe the project’s internal management procedures, detailing the project’s Quality assurance process as well as a detailed Risk evaluation and internal communication tools and mechanisms.

First release of energy-efficient, secure, resilient task-based programming model and compiler extensions

First detailed report of energy-efficient, secure, resilient task-based programming model and compiler extensions. Release of compiler extensions, checkpointing toolset T4.2, T4.4-T4.7

Final release of energy-efficient, secure, resilient task-based programming model and compiler extensions, including FPGA toolchain

Final detailed report of energy-efficient, secure, resilient task-based programming model and compiler extensions. Release of Dfiant, security and replication toolset T4.2, T4.4-T4.7

Report on evaluation and optimizations in the runtime stack

Report on energy-efficiency evaluations and optimizations for energy-efficient, security, and resilience

Final release of the task-based runtime

Final detailed report on the heterogeneous, energy-efficient, secure & resilient task-based runtime

First report on development and optimization of use-cases

First report on the development and optimization of the three use-cases 1. smart home/city, 2. infection research and 3. machine learning. For each use-case the status of the implementations and status/plans for optimizations will be described. Also, the development status of the secure IoT gateway will be reported. T5.2, T5.3, T5.4, T5.5

Report on energy-efficiency evaluations and optimizations for energy-efficient, secure, resilient task-based programming model and compiler extensions

Report of evaluation of energy efficiency optimizations at the compiler level. Release of IDE T4.2-T4.7

Final report on development and optimization of use-cases and integration

Final report on the development and optimization of the three use-cases. The final development and optimization status of the secure IoT gateway will be reported. Also, the results of the integration work of T5.6 will be described.T5.2, T5.3, T5.4, T5.5, T5.6

Communication and Dissemination Plan

This deliverable will detail activities to be undertaken as part of an overall project communication strategy and will provide guidance to ensure that all communications reflect the project’s identity.

Data Management Plan

The DMP will describe the life cycle for all data sets that will be collected, processed or generated by the research project. It is a document outlining how research data will be handled during a research project, and even after the project is completed, describing what data will be collected, processed or generated and following what methodology and standards, whether and how this data will be shared and/or made open, and how it will be curated and preserved. The DMP is not a fixed document; it evolves and gains more precision and substance during the lifespan of the project. It should include the following information: i.Description of Data, ii.Data Collection/Generation, iii.Data management: documentation & Metadata, iv.Intellectual Property Rights and v.Accessibility: Data sharing, archiving and preservation.

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Publications

Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Faults

Author(s): Behzad Salami, Osman S. Unsal, Adrian Cristal Kestelman
Published in: 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2019, Page(s) 242-246
DOI: 10.1109/EMPDP.2019.8671543

A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs

Author(s): Behzad Salami, Osman Unsal, Adrian Cristal
Published in: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, Page(s) 451-4511
DOI: 10.1109/FPL.2018.00085

On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

Author(s): Behzad Salami, Osman S. Unsal, Adrian Cristal Kestelman
Published in: 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2018, Page(s) 322-329
DOI: 10.1109/CAHPC.2018.8645906

Fault Characterization Through FPGA Undervolting

Author(s): Behzad Salami, Osman Unsal, Adrian Cristal
Published in: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, Page(s) 85-853
DOI: 10.1109/FPL.2018.00023

Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

Author(s): Behzad Salami, Osman S. Unsal, Adrian Cristal Kestelman
Published in: 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018, Page(s) 724-736
DOI: 10.1109/MICRO.2018.00064

LEGaTO - towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing

Author(s): Adrian Cristal, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Micha vor dem Berge, Gunnar Billung-Meyer, Stefan Krupop, Wolfgang Christmann, Frank Klawonn, Amani Mihklafi, Tobias Becker, Osman S. Unsal, Georgi Gaydadjiev, Hans Salomonsson, Devdatt Dubhashi, Oron Port, Yoav Etsion, Vesna Nowack, Christof Fetzer, Jens Hagemeyer, Thorsten Jungeblut, Nils Kucza, Xavier Martorell, Martin Kaiser, Mari
Published in: Proceedings of the 15th ACM International Conference on Computing Frontiers - CF '18, 2018, Page(s) 276-278
DOI: 10.1145/3203217.3205339

Security, Performance and Energy Trade-Offs of Hardware-Assisted Memory Protection Mechanisms

Author(s): Christian Gottel, Rafael Pires, Isabelly Rocha, Sebastien Vaucher, Pascal Felber, Marcelo Pasin, Valerio Schiavoni
Published in: 2018 IEEE 37th Symposium on Reliable Distributed Systems (SRDS), 2018, Page(s) 133-142
DOI: 10.1109/SRDS.2018.00024

High performance scheduling of mixed-mode DAGs on heterogeneous multicores

Author(s): Rohlin, Agnes; Fahlgren, Henrik; Pericas, Miquel
Published in: HIP3ES 2019: 7th International Workshop on High Performance Energy Efficient Embedded Systems, 2018

Short Paper: Stress-SGX: Load and Stress Your Enclaves for Fun and Profit

Author(s): Sébastien Vaucher, Valerio Schiavoni, Pascal Felber
Published in: Networked Systems - 6th International Conference, NETYS 2018, Essaouira, Morocco, May 9–11, 2018, Revised Selected Papers, Issue 11028, 2019, Page(s) 358-363
DOI: 10.1007/978-3-030-05529-5_24

Heats: Heterogeneity-and Energy-Aware Task-Based Scheduling

Author(s): Isabelly Rocha, Christian Gottel, Pascal Felber, Marcelo Pasin, Romain Rouvoy, Valerio Schiavoni
Published in: 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2019, Page(s) 400-405
DOI: 10.1109/empdp.2019.8671554

Checkpoint/restart approaches for a thread-based MPI runtime

Author(s): Julien Adam, Maxime Kermarquer, Jean-Baptiste Besnard, Leonardo Bautista-Gomez, Marc Pérache, Patrick Carribault, Julien Jaeger, Allen D. Malony, Sameer Shende
Published in: Parallel Computing, Issue 85, 2019, Page(s) 204-219, ISSN 0167-8191
DOI: 10.1016/j.parco.2019.02.006