Objective
The main objective of the proposed project is to develop methodologies, tools and intellectual property blocks to be integrated in a mixed granularity dynamically reconfigurable SOC implementation platform for the efficient realization of wireless communications systems. The proposed methodology, tools, reusable intellectual property blocks and the mixed granularity reconfigurable implementation platform will be used for the development of systems from the wireless telecom domain including critical parts of a wireless LAN system. Thus the project targets potential system design users from wireless telecom domain, where a good balance between "flexibility" and implementation efficiency is needed during product's life-time.
Objectives:
AMDREL's main objectives are:
(a) Development of systematic methodologies for high level design tasks (such as behavioural optimisation wrt different implementation related factors and especially wrt power consumption, partitioning of targeted functionality to different types of reconfigurable hardware);
(b) Development of reusable intellectual properties (including coarse granularity dynamically reconfigurable hardware blocks, low power fine-granularity configurable logic blocks);
(c) Instantiation of tools for implementation tasks;
(d) Establishment of a dynamically reconfigurable SOC platform with mixed granularity components (fine and coarse grain);
(f) Validation through demonstrators and;
(g) Dissemination and use of results.
Work description:
AMDREL project will adopt an eight workpackages (WPs) workplan to achieve its objectives.
The workpackages will:
- explore target application domain to identify needs for behavioural optimisation and reconfigurability requirements;
- explore reconfigurable platforms to identify requirements for high level implementation oriented optimisation;
- refine the target mixed granularity reconfigurable architecture template;
- select appropriate implementation technology (WP1);
- develop methodology for domain and platform dependent behavioural optimisation;
- develop prototype design support software for behavioural optimisation;
- develop strategy for functionality partitioning between reconfigurable hardware blocks of different granularity;
- develop prototype software for the core of the partitioning approach;
- develop reusable soft intellectual properties for critical modules of the target application domain (WP2);
- design coarse grain reconfigurable hardware blocks and supporting implementation approach (WP3);
- design fine grain reconfigurable hardware blocks and supporting implementation tools (WP4);
- design of interconnect network suitable for reconfigurable platforms and supporting tools (WP5);
- develop demonstrators from the wireless LANs domain (WP6);
- disseminate and use the project results through internet, conferences (WP7);
- manage the project internally and towards the EC (WP8)
Milestones:
- Mixed granularity dynamically reconfigurable SOC architecture template by M9;
- Systematic methodologies for behavioural optimisation and partitioning by M18;
- High level tools and reusable IPs by M28;
- Fine and coarse fain reconfigurable SOC components/interconnect network by M28;
- Real life applications/demonstrators by M36;
- Exploitation/dissemination concluding activities by M36.
Fields of science
- natural sciencescomputer and information sciencessoftware
- natural sciencescomputer and information sciencesinternet
- agricultural sciencesagriculture, forestry, and fisheriesagriculturegrains and oilseeds
- engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technology
Call for proposal
Data not availableFunding Scheme
CSC - Cost-sharing contractsCoordinator
19002 PEANIA - ATTIKI
Greece