Community Research and Development Information Service - CORDIS


DSPACE Report Summary

Project ID: 262798
Funded under: FP7-SPACE
Country: Italy

Final Report Summary - DSPACE (DSP for Space Applications)

Executive Summary:
The continue increase of the demand of on-board processing power needs, highlighted by the new scientific and commercial space missions, raised, in these last years, the strategic importance to rely on mature high performance DSPs. In this context the only actual available space-qualified European DSP device, the ATMEL TSC21020F with a sustained performance of 40 MFLOPS (60 MFLOPS peak) results obsolete and the actual alternative products available on the market (US-made products like Texas Instruments SMV320C6701) are subjected to ITAR restrictions making them not compliant with European space technological “Non-Dependence” and “Independence” guidelines and roadmaps. Therefore from 2007 ESA started different developments in order to target the new high performances European DSP, a flexible and scalable processing system in order to deliver at least 1 GFLOPS performances in a in radiation tolerant modern ASIC technology and to rely on mature and user-friendly programming SW environment.
DSPACE project aimed to provide a developing attempt in the same direction by means of an innovative approach based on the reuse of a mature ground Software Development Environment (SDE) and its adaptation to a new designed space HW System on Chip (SoC) by means of a SW integration layer (CodeOptimizer). In order to optimize the parallel development of HW and SW design within project time and budget constraints, a new approach, based on LISA automated processor designer tool, has been followed granting also a constant interconnection of both design efforts and their mutual improvement through a coherent global output. In order to finalize HW and SW IP realisation the implementation of a system demonstrator and of a set of benchmarks for evaluating DSPACE correct behavior and performances has to be produced. In particular, on demonstrator side, objective has been to emulate the DSP Core into a commercial FPGA to validate its features while, for a better performance contextualization, the base of DSPACE benchmarks implementation has been identified in DSP ESA benchmarks specification ("Next Generation Space Digital Signal Processor Software Benchmark", TEC-EDP/2008.18/RT, December 2008).

According to mentioned approach the goal of DSPACE was to produce a first step through a new high performing Space DSP Core, with capability of 1 GFLOPS @125 MHz in ASIC space technology, conceived to be used both as stand-alone signal processor into embedded systems and as building component in the future scientific missions.
Started in July 2011 and lasting 27 months, the project has been carried on, under SITAEL S.p.A coordination, by a Consortium of two Small and Medium Enterprises (SME), two research organisations and one Large Enterprise (LE) in order to exploit different expertise and complementary skills through mentioned target.
On HW side, the DPACE System-on-Chip has been produced by means of a main processing core implementing a high level of parallelism by means of 8-issue Very Large Instruction Word (VLIW) architecture able to compute up to 8 Reduced Instruction Set Computing (RISC) 32-bit instructions in parallel at every clock cycle. Around this, a minimal and complete set of building blocks has been arranged to supply it with the program, the data caches and the basic needed connectivity.
The Core has been fit on a Xilinx Kintex7-XC7K325T FPGA housed on DSPACE Demo Board an IP demonstrator in line with modern industrial connection standards (cPCI) that can be both installed in a rack and used in stand-alone bench development. It is equipped with 1 GB of DDR2-SDRAM on board Flash memory, EEPROM, SRAM, 2 SpW, 1 USB, 1 JTAG interface, Serial link and GPIO port for off-board communication. A mezzanine board can be connected to the main board providing system with additional links.
On SW side the implemented DSPACE SDE is based on an open source GCC distribution and is a complete, easy to use and reliable suite with standard functionalities allowing programmers to be able to write code for the new processor the way they are accustomed to, using well-known interfaces as the user interface derived from DSPACE structure (DSPACE C Compiler, DCC) operating as a static binary translation compiler and enriching GCC command line with DSPACE specific options. DSPACE SDE is provided with a Graphical User Interface based on an Eclipse Plug-in allowing programs development in a windows-like based environment.
Starting from mentioned ESA specification, a complete set of benchmarks has been developed that allowed correct testing and validation of the whole DSPACE system.
DSPACE technical tasks have been supported by constant dissemination activity (creation of Project Website and Brochure, participation to meetings, events and publications) that, together with a constant space market analysis and device contextualisation, contributed to collection of main audience feedbacks for defining the right business model and exploitation strategy for DSPACE.
The underlined deep gap between system actual development and space market needs makes difficult to envisage short time device commercialisation but it not excludes possible future related business once DSPACE maturity, level, knowledge and usage will be raised, as happened for other similar developments like LEON.
To this purposes within the end of 2013 DSPACE IP package will be distributed for free for pure academic and research purposes on Design and Reuse website. It is expected that the results of the project will influence first a wide community of researchers, developers and users at national, European, and international levels. In a second time it is expected also the results of the project to influence a wide community in the space market including equipment manufacturers, software developers, system integrators, research and development, academia providing expected contribution to European space technology “Non-Dependence” and “Independence” needs.

Project Context and Objectives:
The new scientific and commercial space missions aim to manage always bigger data flows, requesting an high on-board numerical calculation capability. In this context, the on-board data processing represents one of the most critical points/issues for any spacecraft in order to exploit the available transmission bandwidth. This increase of calculation capability and speed is requested at every system level: from the control execution to data processing, from data transfer to their storage. Particularly, applications requiring computer graphics calculation or image/video processing are high expensive in terms of required processing capabilities, memory access rate and storage size. In space applications, complicated processing algorithms are needed in several fields: earth observation and surveillance, Synthetic Aperture Radar (SAR) imaging, planetary observation, and emerging manned space transportation system for human-interface displays.
Mentioned increase of on-board processing power need cannot be satisfied anymore by the only available space-qualified European DSP device, the ATMEL TSC21020F. This rad-tolerant DSP processor is at present obsolete having a sustained performance of 40 MFLOPS (60 MFLOPS peak) and its end-of-life having been announced for 2011/2012.
Possible actual alternatives on the market to face with growing space DSP performance needs are based on US-made products (i.e. Texas Instruments SMV320C6701) however subject to export restrictions (ITAR). This condition significantly limits European ambitions, space policies and restricts technological and strategically partnerships with emerging countries such as China and India.

In relation to European main guidelines for driving actual and future space developments, as stressed since 2009 in EC-ESA-EDA Joint Task Force meeting (6th March 2009), two are the concepts to be taken into account in the next space technology developments:
• “Independence”: all needed space technologies shall be developed in Europe
• “Non-dependence”: Europe shall have free and unrestricted access to any required space technology.

In particular, the second point strongly limits the usage of ITAR alternatives to TSC21020F and triggers the starting of different optional developments. In this context, ESA produced effort since 2007 underlining as a crucial and strategic space roadmap the development of a European radiation tolerant high-performances general-purpose DSP processor ("Next Generation DSP round table", ADCSS07). Two following key requirements have been established:
• DSP performances higher than 1 GFLOPS in radiation tolerant ASIC technology
• High quality DSP application development environment and DSP SW libraries.

After this, various studies and technical activities have been started that identified different additional requirements for the next generation DSP: radiation hardness TID > 100 Krad, EDAC memory protection, support for space standard interfaces as SpaceWire (SpW), high quality software development environment…
In order to get as near as possible to the design of a processor system with such characteristics different possible solutions have been stated according to three main following approaches:
• COTS processors (i.e. TI6727) radiation hardening by computer board at HW/SW level
• Multi-Core microprocessor realization (i.e. LEON + specialized computation units)
• Commercial DSP porting to ASIC rad-hard technology.

In last years, different Technology Research Programme activities started exploring listed options highlighting pros and cons of each approach without individuating a univocal solution for the problem for different reasons.
In particular COTS based computers activities (i.e. "High Performance COTS based Computer" and "High Performance Payload Digital Signal Processor" ESA projects) have the advantage to deliver good performances systems in the short time, but that cannot be scaled into small application and are destined to suffer problems coming from the even shorter lifetime of the ground components with the risk of early obsolescence.
The multicore approach (adopted for example in "Massively Parallel Processor Breadboarding Study" activity) provides many advantages in particular for what regards processing performances and flexibility/scalability, but suffers issues related to IP rad hardening and Software Development Environment (SDE) maturity.
Undertaking of the third solution (as investigated in "Next Generation DSP Trade-off Study" ESA activity) encounters as main obstacles first the technology gap that makes the automatic porting of a ground DSP into space technology difficult and then related high costs due not only to DSP licensing but also to the effort to be produced for its space tailoring. Mentioned approach represents the best option for getting near to listed key requirements but important underlined related issues depict it as long term available solution (not before 2018).
In this context and in function of mentioned EU critical need of space technological “independence” and “non-dependence”, “DSP for space applications” project (DSPACE) has been conceived proposing as alternative solution the development of a new Digital Signal Processor component for space applications. The innovative approach is based on the aim to transfer the features and the background knowledge bound to a commercial product into a space device without performing a complicated ground to space technology porting.
The goal of DSPACE was to develop a new high performing Space DSP Core, with capability of 1 GFLOPS @125 MHz in ASIC space technology, conceived to be used both as stand-alone signal processor into embedded systems and as building component in the future scientific missions.
Started in July 2011 and lasting 27 months, the project has been carried on, under SITAEL S.p.A coordination, by a Consortium of two SMEs, two research organisations and one Large Enterprise (Figure FR1). DSPACE partners cover whole range of needed expertise for addressing the achievement of the project’s goals and consortium has been designed in a very complementary fashion. The partners, coming from Italy, Belgium and Germany have already cooperated in a number of projects so that well-established relationships supported the collaboration. The inclusion in the Consortium of two research institutes gave the possibility to distribute the results of the project as well as collect information on the newest trends in this area through their typical network activities. On the other side, the industrial partners offered an ideal platform for collecting the industrial requirements and for discussing the results. A key success factor of the project has been the involvement of well-motivated and qualified SMEs. Knowledge of mutual characteristics of partners created a strong and balanced consortium capable to run a collaborative project of high innovative added value.
According Consortium belief the technical approach to be adopted for designing a new space digital signal processor has to be mainly concentrated on the fact that, regardless the device intrinsic features (FLOPS, bandwidth) and requirements, the success of a new processor development is due to the availability of a complete and reliable programming platform. However the effort needed for such SDE design is much larger than that for the HW Core development and production of a new SDE could not be realistically afforded from scratch nor for the amount of required funding neither for the development timings. This also because the reliability/maturity level of a SW tool usually derives from its users experience (and feedbacks), and since the space programmer community is much smaller than the commercial DSP one, the consequent integration timing may became very long. Moving from these considerations, the technical approach proposed by DSPACE aimed to re-use large part of the SDE of an already existing commercial reference DSP. Once selected target SDE and reference model architecture, the possibility to adapt it to the space designed DSP should be achieved by means of creation of an integration SW layer based on a Code Optimiser (Figure FR 2). Code Optimiser has to grant compatibility at binary code level with reference architecture translating the output of the high level-programming reference compiler into assembly code of the target space DSP core and playing also a key role in the final success of the entire project by means of an off-line code pre-processing to mitigate the architecture aspects that may be too difficult or costly to be implemented in HW with actual space technology.

Additional following targets providing guidelines for project developments have been defined by consortium:
• DSP core scalability for numerical computation into space missions
• DSP core easy flexibility for integration in different technologies (FPGA or ASIC)
• DSP core multi-purpose efficiency in terms of sustained performances with different benchmarks representative of future space mission requirements
• HW design focus on sustained data processing capabilities instead of on the peak processing power
• SW device focus in order to deliver a “friendly programmable” device for its final user, based on common or easy to learn programming tools.
In the perspective that a new processor has to be largely used to reach a sensible reliability degree before being fitted into an ASIC product, DSPACE debug, testing and validation have been defined as key objectives to complete design effort through the achievement of project goals.
To this purpose, the implementation of a system demonstrator and of a set of benchmarks in order to evaluate DSPACE correct behaviour and performances has to be produced during project development.
The base of DSPACE benchmarks implementation has been identified in DSP ESA benchmarks specification ("Next Generation Space Digital Signal Processor Software Benchmark", TEC-EDP/2008.18/RT, December 2008) to be analysed and to drive related development in order to correctly target a space-environment-contextualized system validation.
On demonstrator side objective has been to emulate the DSP Core into a commercial FPGA to validate its performances. To this purpose, an advanced prototype board housing an instance of a selected suitable FPGA device for Core fitting has to be produced and made available to consortium partners responsible of validation activity. Prototype has to be designed taking into consideration the interfacing needs proper of space developers and exploiting, when possible, available implementation solutions to extend the opportunities of future development activities on DSPACE.

Therefore, project has been structured to be composed of three following HW/SW coordinated main design activities:
• the design of the high performances DSP Core suitable to be realized with actual European space qualified technology and the realization of an FPGA prototype representative of all its features
• the selection of reference SW suite and the development/integration of a Code Optimizer to be inserted in a standard tool-chain including all the necessary Software Development Environment for the proper functioning of DSP
• the selection of space significant benchmarks to provide additional concrete criteria for the evaluation of the candidate architectures, to be developed in parallel with the DSP design in order to contribute to critical decisions during the implementation and validate the final performance of the DSP.
Finalisation of project expectations has to be produced by means of a correct and extensive dissemination and promotion activity (i.e. Project Website and Brochure realisation, events and publications participation…) about in progress development outcomes and targets. In parallel to this, the continuous monitoring of the device position in space market and related business model definition has to be performed in order to strengthen previous activity through the definition of the most proper DSPACE exploitation strategy.

Project Results:
4. Description of the Main S&T Results/Foregrounds
Technical project activity leading to the realisation of DSPACE IP has been carried on by means of the parallel implementation of the HW and SW sections of the device. Mentioned developments have been produced in a coordinated fashion by two main responsible consortium sub teams (HW and SW partners) in order to produce in progress crossed contributions for a better refinement, consolidation and integration of the whole designed system. Here below main related project outcomes are depicted.
On HW side, the designed DPACE System-on-Chip (SoC) architecture (Figure FR 3) is composed of a main processing core and a minimal and complete set of building blocks arranged to supply it with the program, the data and the basic needed connectivity.
The processor is equipped with basic on-chip peripherals able to provide I/O and external control capabilities. The system is conceived to work with cache memories both for instructions and data, while all communications with the external DDR2 SDRAM memory (i.e. in case of cache miss) are driven by the on-chip Direct Memory Access (DMA) controller through the DDR2 memory controller.
The information exchange (commands, data, programs, etc.) between the DSPACE chip and the hosting system leverages two SpaceWire interfaces that are the natural choice in the space field. In particular, these interfaces allow the interaction with the on-board control logic and the memory controller bypassing the DMA. Two Advanced Microcontroller Bus Architecture (AMBA) standard busses as well as dedicated busses are involved within the chip.
Depending on the final Flight Model technology, Triple Modular redundancy (TMR) and voting logic could be necessary to protect all the registers, while the on-chip memories and all the external memory interfaces are already protected via Error Detection And Correction (EDAC) codes for Single Error Correction/Double Error Detection (SEC/DED) on a block of data.

In the detail, the high-level DSPACE System-on-Chip blocks are the following:
• The Data Processing Unit (DPU), the real core of the DSP design on which the DSPACE project is focused, being in charge of fetching, decoding and executing the program instructions coming from the Instruction cache (I-Cache) using the data provided by the Data cache (D-Cache). It is an “ordered and symmetric” processor and features a Very Large Instruction Word (VLIW) architecture with a high level of parallelism. To improve the performance goal, the DSPACE DPU is based on 8-issue VLIW architecture able to compute up to 8 Reduced Instruction Set Computing (RISC) 32-bit instructions in parallel at every clock cycle. Assuming a conservative ASIC frequency of 125MHz, it should ensure near 1 GOPS. Each functional unit reads directly from, and writes directly into, the register file. Some limitations inside the register file between two set of locations and the specific execution unit ports reduce the internal routing complexity. The DPU is composed of the following macro-blocks:
o The Program Flow Controller constituted by the Fetch and Decode units in charge of retrieving instructions from the I-Cache and dispatching them to the execution units together with the operands (the assignment among instructions and execution unit is made explicit into instruction operation codes encoding so that the HW support for their dispatch is minimal)
o Large multiport register file in charge of storing operation results
o Eight execution units: 2 Floating Point Multipliers (FP MULs), 4 Floating Point Arithmetic Logic Units (FP ALUs), 2 Address Generation Units (AGUs) in charge of practically performing computational operations
o Control and Status register file constituted by collection of 20 registers dedicated to control the status of the operations computation, the interrupts management and the addressing mode configuration.
All the execution units are planned working as pipelined operators assuring a throughput of one operation for cycle. Supported operands are compliant with the 32-bit 2’s Complement Fixed-Point and IEEE 745 single precision Floating-Point formats.
The instruction set contains148 instructions: 90 assigned to the FP ALUs, 24 to the FP MULs and 34 to the AGUs. All instructions can be executed conditionally depending on the value of a flag in the operational code and the content of some registers of the register files devoted to this function.
The DPU is designed with a single-cycle throughput and it implements a 7-stages pipeline that is stalled in case of cache misses, both for instructions and data, until the entire block of missing data has been transferred from the external main memory to the involved cache via the DMA controller.
The control and status register file elements report the status of the execution of the instructions (i.e. carry, saturation, etc.) both for Fixed-point and Floating-point operations, allow to control the processor behaviour (i.e. addressing mode of AGUs, rounding mode, etc.) and finally the interrupts management.
• The Instruction Cache (I-Cache) and the Data Cache (D-Cache). In order to keep the design simple, two separated single level caches have been inserted for instructions (I-Cache) and data (D-Cache). Data and Instruction Caches are the modules in charge of providing the DPU with instruction and data flows needed to supply the 8 execution units in parallel satisfying the requirements of low latency and high bandwidth.
Both caches are implemented with a direct-mapping strategy. The D-Cache looks out a more critical design for the need of three ports working in parallel (2 ports for DPU data-paths and 1 for the DMA). This implied the availability of dual port memory macro-cells support, and a complex memory blocks management (using double frequency logic) to compose them in a resulting three/four port memory.

Independently from the internal organization of these Caches all these memories have been equipped with the error detection and correction code (SEC/DED EDAC).
• The DMA controller. A DMA engine has been inserted to transfer data between the caches and the Memory Controller interface. The control of this data-path has been moved outside the caches to give the programmer the possibility to directly manage the local data “pre-fetch” and “save” operation with a predictable paradigm. In fact, the DMA controller is mapped in the I/O space of the DPU and the programmer has the possibility to start DMA transfer activating the controller via software instructions. The DMA controller can be triggered by a reset of the DPU, a Cache-miss event and mentioned direct programmer interaction aimed to handle the cache data pre-fetch to prevent miss conditions and keeping the processor timings predictable. Furthermore, the DMA controller holds a counter for succeeded transfers that contributes to the Interrupt Request (IRQ) generation.
• The Memory controller, able to manage the transfers that involve the external DDR2 SDRAM memories. The Memory Controller interface has to be intended as the DSPACE interface towards the on-board memory containing the overall program and set of data to be processed. It can be driven both by the hosting system via the SpaceWire link and the internal DMA Controller. The port towards the main memory is able to manage a 64-bit DDR2 memory while the connection with the DMA exploits the Sync Bus together with the Memory bus. The Memory controller module also holds the EDAC logic for protecting the First In First Out (FIFO) system embedded into Synchronizer and the DDR2 memory.
• Two redundant SpaceWire links, for the communication with the external host system both for programming and control purposes. Two instances of the SITAEL Remote Memory Access protocol-SpaceWire (RMAP-SpW) core are embodied in the SoC mounted in the AMBA memory space. Each module is composed of a SpaceWire link interface, a RMAP receiver and two independent AMBA AHB Master and Slave interfaces. The RMAP receiver filters all the incoming packets. It recognizes the remote memory access requests and transfers them on the AMBA bus through the AHB Master interface. Then it automatically sends back on the SpW link the required acknowledges. The incoming non-RMAP packets are forwarded toward the SpW link without any filtering.
• A Control Logic, which drives the DPU input status signals. It is possible to pilot these lines from the external host system via the SpaceWire ports.
• The Advanced Peripheral Bus (APB), enabling the DPU (master) to interact directly with the on-chip peripherals (slaves) that represents its own I/O space: DMA, Control Logic, Caches EDAC, DDR2 EDAC, Synchronizer EDAC and SpaceWires. All the peripherals memory-mapped registers dedicated to the configuration and the I/O operations are mapped in the APB space.
• The multi-master Advanced High-performance Bus (AHB), for high performance communication among the host system, the memory controller and the control logic. It connects the SpaceWire interfaces (the external environment) with the Control logic, Memory controller and AHB/APB bridge.
• The AHB/APB bridge, controlling the on-chip peripherals directly from SpaceWire interfaces. It can only act when APB bus is not granted to the DPU (DPU stalled).
• The internal Memory/Sync Busses, in charge of moving data between the DMA controller, the Synchronizer and the Memory controller towards the external main memory. Both instructions and data extracted from the main memory uses these buses. Indeed the Instruction Bus and the Data Bus are connected respectively with the I-Cache and D-Cache controllers and move instructions and data among the caches and the DMA in case of miss or programmatic transfers.
• The Synchronizer, managing the synchronization between the DPU clock domain and the DDR2 clock domain. The Synchronizer links the Sync Bus (DMA-Synchronizer) with the Memory Bus (Synchronizer-DDR2 controller).

The core embodies a Universal Asynchronous Receiver-Transmitter (UART) interface that acts as an AHB master and gives the full remote access to the DSPACE architecture.
In the DSPACE architecture there are three following main kind of interrupts, served with different levels of priority and originating by on chip or off chip source:
• Reset. It is the highest priority interrupt, generated by an external pin and forcing to stop the current execution and to move the DPU to a well-known condition. It is not possible to disable this interrupt.
• Non-maskerable. It is the second priority interrupt. It is generated by an external pin like the reset one to alert the DPU of a serious hardware problem.
• Maskerable. It is the lowest priority interrupts category. Eight maskerable interrupts are available in an additional priority order. They may be generated by an external pin, on-chip peripheral and via software. These interrupts can be served only if they are generally and individually enabled.

The design of the DSPACE SoC and related VHDL database has been produced according following innovative approach. The DPU has been defined exploiting the feature of the LISA suite developed for Synopsys by RWTH Aachen University (member of DSPACE consortium). LISA is an Architecture Description Language (ADL), which allows describing the processor’s behavior as well as its structure including register files, execution units, pipelines and memory on a higher abstraction level. From this unified specification, a complete SDE can be generated, including assembler, linker, instruction-set simulator and a SystemC wrapper model. Furthermore, synthesizable VHDL or Verilog code can be generated from the same reference. This feature ensures the consistency between generated software tools and generated hardware and dramatically improves productivity and quality of the developed processor. This fastened development cycle allows an efficient modeling and architecture exploration by analyzing different design trade-offs while keeping software tools and hardware development in synchronization automatically. In this way, design decisions can be taken based on synthesis results. Synopsys Processor Designer, the product build around the LISA 2.0 language, is an integrated, embedded processor development environment. It supports the development of custom processors and programmable accelerators. It provides a rich set of profiling and simulation capabilities and debugging facilities for the processor model itself as well as software running on the developed processor. Exploiting LISA features, HW partners of DSPACE consortium have been able to deliver an high-level quality product basing the design of the SoC on a short-time-available reliable Core (DPU provided by LISA) saving an important amount of time respect to the traditional development approach (not possible for the whole system within time and budget allowed by project activity) that has been dedicated to “hand-made” DPU VHDL refinement and implementation of the rest of VHDL needed building blocks. In addition to the fast system prototyping benefit, this approach gave the advantage of VHDL database deep compliance with the corresponding SW tools (Assembler, Linker, Instruction Level Simulator, SW debugger) providing desired deep interaction and in progress alignment between HW and SW developments. This allowed system optimization to be started at an early stage and improved and easily carried on during the FPGA prototyping and validation activities.
Synthesis and fitting exercises have been executed both for the full System-on-Chip and its parts to evaluate the effective resource budget and the operating frequency of the full design. Taking as space reference the qualified Xilinx Virtex5-XQR5VFX130, few iterations have been produced on the resource budget in order to perform related DSPACE Core fitting. This allowed the selection of the target ground equivalent FPGA and the related IP demonstrator prototyping.
The DSPACE Demo Board has Compact Peripheral Component Interconnect (cPCI) 3U size and embodies a Xilinx Kintex7-XC7K325T FPGA allowing an easy fitting of the DSP Core. Housed Xilinx FPGA is a modern high performing and flexible device particularly suitable for high computation needs to be addressed with low power consumption and costs (main modern requirements for space market oriented demonstrators). The complete SoC occupies about 35% of the resource budget on this device.
The board is in line with modern industrial connection standards, can be both installed in a rack and used in stand-alone bench development. It is equipped with 1 GB of DDR2-SDRAM on board Flash memory, EEPROM, SRAM and SORDIMM interface for DDR2-SDRAM together with PCI, SpW, Universal Serial Bus (USB), Joint Test Action Group (JTAG) interface, Serial link and GPIO port for off-board communication.
In particular two SpaceWire, one header connector for RS232 communication links (for remote control and program upload/download) and a JTAG interface for the FPGA programming are the main interfaces available on-board.
According to mentioned different connection options, two following versions of the DSPACE Demo Board have been implemented. Together with the cPCI version, suitable for being housed in a compatible crate, a stand-alone desktop version has been produced that has been used by consortium partners for system validation activity (Figure FR 4).
Desktop version is enclosed in its ABS case including a fan coiling system and is provided with the 5 Volt power adapter and the DSPACE ribbon cable for FPGA programming. Removing the ABS case cover, the JTAG connector is accessible in order to program the FPGA (Figure FR 5).

The DSPACE Demo Board front panel holds following items:
• Two DB-9 connectors
• Two SpaceWire connectors
• One General Purpose Input/Output (GPIO) connector
• One USB connector
• Three LEDs (red, amber, green)
• One reset button.
Its back panel holds a 5V DC power connector and one cPCI connector.
The reset button is used for resetting the internal state of the DSPACE Core while the three LEDs have status signalling functions in relation to power supply (green), USB link (amber) and user defined (red) parameter.
At present the USB (and related LED), GPIO and cPCI connectors are not used for DSPACE project. They have been inserted in order to deliver a flexible device for further development activities on the IP. Always in this context, the design and production of a mezzanine board housing additional communication equipment and links for future improvement, utilization and development of DSPACE has been performed.

The manufactured mezzanine board contains a FPGA acting as bridge between the DSPACE Demo Board and the following communication buses:
• Two MIL-STD-1553B buses, interfaced via Twinax BJ77 bulkhead connectors
• Two Controller Area Network (CAN) buses, interfaced via RJ-45 connectors
• Two Inter Integrated Circuit (I2C) links, both interfaced via front panel header connectors.
DSPACE Demo Board is provided with expansion connectors allowing the mounting of the mezzanine board.
User interfacing with the DSPACE Demo Board is allowed by a SW suite (DSPACE High Level Driver) running on Linux O.S. based Personal Computer.

On SW side the implemented DSPACE Software Development Environment (SDE) is a complete, easy to use and reliable suite with standard functionalities allowing programmers to be able to write code for the new processor the way they are accustomed to, using well-known interfaces. In this context, the use of existing software when possible has been exploited according to target development aim.
Two of the main three bases of the whole system tool chain and related implementation/integration are the Assembler and Linker layers. They enable an application to be executed on the target architecture modelled in LISA and their generation is completely automated, based on the LISA source code, without need of manual interaction or specification. They are used just like other well-known assemblers and linkers for a host target machine. Linker and Assembler represent also the deep link between HW and SW systems allowing however a self-standing software development in the DSPACE environment. In this context programmer can realise applications directly in DSPACE assembly language and feed them to Linker/Assembler chain in order to produce the executable files. However, this approach is not a good solution for developers. SW realisation in this way requires a lot of time, it is hard to maintain and difficult to implement.
Therefore, starting from the existing DSPACE Assembler and Linker, a C source compiler has been integrated in the whole tool chain in order to target expected programming suite features.
To this purpose the analysis of many different SDEs (e.g. G21 package, VisualDSP++ development software, TriMedia SDE) in order to determine a suitable reference for DSPACE tool-chain led to the selection of an open source distribution (GCC) because of licencing issues that prevented from using commercial ones outside of HW produced by their same manufacturer, and therefore for DSPACE activity. Selection of reference GCC distribution provided DSPACE with the needed C source compiler base for following development and integration of the whole tool-chain.

The final DSPACE SDE (Figure FR 6) is composed by
• GCC C Compiler (GCC). This component produces the reference architecture assembly from the C source code written by the programmer.
• Glue Software. This component is the “Ground-to-Space Code Translator” in the sense that it “translates” the reference assembly architecture generated by GCC layer into “DSPACE Linear Assembly”. The DSPACE Linear Assembly is the abstract-linker-interface between the ground and the space DSP architectures. It abstracts ground-HW linked assembly produced by GCC providing a code independent and unaware of the hardware characteristics (as an example, it ignores pipeline timings, functional units and machine registers) allowing the programming flow to be easily adapted and optimised to the DSPACE DSP architecture by following layer. The Glue Software consists of the following modules:
o Parser. It takes in input the reference architecture assembly file and produces an in-memory internal representation of the assembly program.
o Core. It takes in input the internal representation generated by the Parser and applies a number of transformations to produce an intermediate assembly suitable for the following layer optimization process. Core Module performs the Static Single Assignment analysis (SSA) for removing dependencies from the reference architecture (e.g. number and register naming, functional unit constraints, register spilling etc.). The output of the Core is still an in-memory internal representation of the program that is expressed using the same data structures generated by the Parser.
o Translator. It takes in input the internal program representation generated by the Core and produces a file containing DSPACE Linear Assembly.
• Code Optimizer. This component takes in input the DSPACE Linear Assembly produced by the Glue SW and produces optimized code for the DSPACE processor. Linear Assembly format contains DSPACE machine instructions not aligned in a sequence and assumes non-pipeline virtual machine that executes one instruction at a time. In order to get machine code for the DSPACE processor, linear assembly code should be mapped onto the parallel clustered VLIW architecture. The CodeOptimizer tool performs this mapping process. It takes DSPACE Linear assembly (.LS) as input and produces parallel DSPACE assembly (.S) as output. It is based on the widely known Low Level Virtual Machine (LLVM) Compiler Infrastructure. The transformation from Linear to Parallel assembly has similarities with traditional DSP code generation done in compiler back-ends. The major difference of Code Optimizer comparing with compiler back-ends is the lack of instruction selection due to Linear Assembly input. Linear Assembly already contains DSPACE processor instructions and hints about optimal register allocation provided by earlier GCC and Glue Software interactions. Parallel DSPACE assembly output can be further translated into object code or executable image using other tools such as LISA-based DSPACE assembler and linker. Code Optimiser layer is formed by following blocks (Figure FR 7):
o Parser Module. It reads input files, manages header files, performs lexing and parsing, and finally generates the Intermediate Representation (IR).
o Analysis Module. It checks constraints, builds data dependency graphs and other data structures that are necessary for further optimizations.
o Register Allocation. It checks cross-path constraints and assigns parameters to physical registers to avoid data access problems.
o Instruction Scheduling. It reorders instructions to face pipeline hazards and avoid processor stalls.
o Code Compaction. It is integrated with scheduling and assigns operation to functional units.
o Peephole optimizations. It transforms instructions into more efficient equivalents or removes redundant code.
o Serialization. It produces output parallel assembly file.
• Assembler and Linker. LISA-based tools translating the DSPACE assembly into object code and executable image.

The integration approach leading to the definition of the DSPACE tool-chain provided following advantages:
• The design is modular, powerful, flexible and easy to maintain and test:
o Possible changes to SDE software layer impact only on Glue Software component
o Possible changes to the hardware impact only on Code Optimiser component.
• DSPACE Linear Assembly decouples hardware from software (pipeline, registers, functional units, scheduling can be ignored).
• DSPACE Linear Assembly can be written manually. This allows a developer to write C code portions in Assembly for an increased efficiency and also to quickly write test programs.
• The definition of a Linear Assembly in conjunction with a Code Optimiser module is a standard and tested approach that is also envisaged by important manufacturers.
The user interface derived from DSP SDE structure is the DSPACE C Compiler (DCC). DCC is the DSPACE software component that calls the modules of the tool-chain (Figure FR 8). It globally operates as a static binary translation compiler and enriches GCC command line with DSPACE specific options.

From a logical point of view, the DCC compiler is composed of the following stages:
• Stage1 - Syntax Check. During the Syntax Check the GCC compiler is called in order to produce reference architecture assembly. All errors and warnings detected by the GCC are reported to the user. GCC successful completion generates a program internal representation in the form of an assembly program class allowing the beginning of following stage.
• Stage2 - Transformation Phase. During the Transformation stage, the internal representation generated by previous step is used as input to the Core Module that applies a sequence of transformations. The result of the transformation is an internal representation of Linear Assembly. Syntax is still in reference architecture format. This phase ends translating the reference architecture syntax into DSPACE Linear Assembly syntax.
• Stage3 - Optimization Phase. During the Optimization stage, the DSPACE Linear Assembly is processed in order to obtain optimized parallel and rescheduled DSPACE assembly.
• Stage4 - Object Code Generation. During this phase, the binary code is generated using the compiler provided by LISA.

DCC production has been completed by a Graphical User Interface (GUI): the DCC Eclipse Plug-in.
Due to Linux development platform, the Eclipse tool has been the natural choice in terms of portability and compatibility. The DCC Plug-in for Eclipse allows developers to create DSPACE applications using windows- style interfaces (Figure FR 9) instead of applying parameters via command line.
DSPACE plug-in system works on any Linux distribution running Eclipse version 3.5 or above and Java Development Kit (JDK) version 6 or above.
Always on SW side and in parallel to the SDE development, a set of software benchmarks that are representative of realistic DSP use in space has been specified, developed and executed on the DSPACE Demo Board.
The starting point for their definition has been represented by the DSP software benchmarks specification established by ESA in the document "Next Generation Space Digital Signal Processor Software Benchmark" (TEC-EDP/2008.18/RT. December 2008). The ESA document identifies a set of application and kernel benchmarks and specifies associated requirements for software implementation, test setup, documentation of results and performance extrapolation.

According to mentioned document five following benchmarking scenario are envisaged:
• Benchmark B1: I/O Performance
• Benchmark B2: Analogue Data Acquisition, Processing and Output
• Benchmark B3: Image Data Compression and Packaging
• Benchmark B4: Onboard Data Processing Case 1
• Benchmark B5: Onboard Data Processing Case 2
While the ESA benchmark specification has formed the basis for the DSP benchmark development, some tailoring of it has been necessary due to the particular constraints of the DSPACE project.
The development of the DSPACE benchmarks has started from the implementation of kernel algorithms, which are the building blocks to be used for subsequent implementation of the complete benchmark set. The main kernel functions identified in the benchmark applications are: FIR filter functions, FFT functions, and data compression algorithm (CCSDS Lossless Data Compression). In addition, some auxiliary functions also have been provided as building blocks for efficient implementation of DSP applications (for example routines for data copy, or for conversion of data between integer and floating point formats). Most of these functions (FIR filter, FFT, and simpler routines) are normally part of an optimized DSP library: the lack of such a library for the DSPACE processor implied the need to develop them. The kernel functions have been developed either in C language or in DSPACE assembly. Writing assembly code allowed obtaining optimal performance: applying code optimization techniques such as loop unrolling and SW pipelining, the full potential of the resources in the DSP data-path has been exploited.

Each kernel function has been tested by execution both on the LISA processor simulator and on the DSPACE Demo Board. For each kernel function, a unit test program has been developed, together with appropriate input test vectors and output reference vectors. The list of implemented functions is the following:
• Fast Fourier Transform (FFT) function
• Real Finite Impulse Response (FIR) function
• Complex FIR function
• Lossless Data Compression
• Floating point to signed integer conversion function
• Signed integer to floating point conversion function
• Signed short to signed integer conversion function
• Signed integer to signed short conversion function
• Move function

All of the developed kernel functions passed their tests when executed on the simulator and on the DSPACE Demo Board
The benchmarks have been executed in a setup consisting of a prototype platform and a laboratory PC (Figure FR 10). The prototype platform is the DSPACE Demo Board, with the FPGA programmed with the DSPACE DSP Core and providing the processor with the HW resources (e.g. memories, data communication interfaces…) required to support the execution of the benchmark programs. The laboratory PC, also known as benchmark support unit, is a PC running a standard Linux distribution and equipped with specific HW interface devices (for connection with the prototype board) and related software drivers.
The software product consists of two parts: the Benchmark Software and the Support Software. The benchmark software is executed by the DSP CPU on the DSPACE Demo Board and it relies for its execution on functionalities provided by the board support package. The support software is executed on the laboratory PC and relies on the services of the underlying Operating System, as well as on drivers and libraries required to operate specific hardware peripherals (e.g. link interfaces) with which the PC is equipped.

Following benchmarking scenarios have been implemented and run on the validation setup:
• I/O performance benchmark scenario. This benchmark application derives from the benchmark scenario B1. The purpose is to quantify the performance of the processor data communication interfaces. The DSPACE Demo Board provides two SpW link interfaces running at 100 Mbps. This benchmark application establishes bidirectional transmission on one of the two available SpW ports of DSPACE. No simultaneous use of the two SpW ports has been implemented. SpW packets filled with dummy data are generated by the Benchmark Support PC and sent to the DSPACE processor, and viceversa. On both the PC and DSPACE processor, packets are created reading data from memory (data is not routed from one SpW port to the other). In the DSPACE SoC, each SpW core is connected to both the AHB bus and the APB bus. The SpW core is a master on the AHB bus and a slave on the APB bus. In this benchmark application, the APB bus interface is used to move data between the SpW core and the memories, passing through the processor. The DSPACE processor reads and writes the SpW core receive buffer and transmit buffer, which are accessible as registers on the APB bus. Each read and write access transfers a 32-bit word.
• Basic DSP processing scenario. This benchmark application derives from the benchmark scenario B2. The purpose of this scenario is to assess the performance of the DSP in a typical application of analogue data acquisition, processing and output. Since the DSPACE prototype board does not provide Analogue to Digital Converter (ADC) and Digital to Analogue Converter (DAC) chips, the analogue acquisition would have to be replaced by a simulated external data source providing data from interfaces that are fast enough not to constrain the processor’s throughput. Input data to the processing consists of a sequence of 16-bit data words (16-bit signed integers in 2's complement format). This sequence is provided as part of the executable image (initialization of C arrays). Benchmark scenario B2 prescribes seven load cases. Two of them have not been implemented. Load case 1 has been ruled out because it focuses on the performance of the ADC/DAC interfaces, which are not present in the set-up. Load case 6 also has been ruled out, as its unusual FFT length (1960 points) would have required significant algorithm research. Load cases 2, 3 and 4 consisted of filtering the input data with FIR filters of length 16, 64 and 256 taps respectively. Load cases 5 and 7 consisted of computing the FFT with 1024 and 4096 points, respectively. The correct execution of the processing in this benchmark scenario has been verified by inserting some “correctness check code”. When executing the benchmark application to measure performances, the “correctness check code” has been disabled using conditional compilation, so that it does not affect the performance.
• Onboard data processing scenario. This benchmark application derives from the benchmark scenario B4. The purpose of this scenario is to assess the performance of on-board data processing. To this aim an input data of 16-bit integer (signed 2’s complement fixed-point rational) complex data is sent to DSPACE via SpW packets of length 320 bytes each, thus each packet contains 160 16-bit input samples, i.e. 80 complex values. The data of each packet is processed and the corresponding output is transmitted back to the PC in a packet. On DSPACE, the SpW I/O is handled in the same way as in the I/O performance benchmark scenario. The processing consists of filtering, decimation and compression.

Benchmarks definition and implementation completed the SW development related to DSPACE IP. Their availability together with that of all the different described parts of the DSPACE IP allowed correct testing and validation activity regularly carried on in the last part of project development.
In addition, even if ASIC design/implementation was not envisaged by project activities, the possibility to project DSPACE outcomes through a target future space realisation and to provide a prevision of related possible system performances has been taken into account.
To this purpose a synthesis estimation attempt has been performed on space ASIC STM 65nm technology. In particular a maximum rate of 325 MHz (162 MHz for the DPU) has been obtained for the ground technology. In order to translate results obtained in space domain, an opportune derating factor has been applied (0.7) obtaining a maximum clock frequency of 227 MHz (113 MHz for the DPU) with a performance above 900 MOPS and a complexity of about 350 Kgates (272 Kgates for the DPU).

Potential Impact:
In order to fully exploit the potential acquired in the project, communication activities have been carefully planned and monitored during project lifetime.
The main task of these activities has been to disseminate the scientific and technological knowledge acquired in the course of the project among the participants, the space community and a wide general community. The principal objectives were:
• to raise awareness of the project and its results
• to augment the body of knowledge on the matter
• to facilitate further related research and development
• to define the correct positioning of the DSP on the market and select most appropriate business model and exploitation strategy for main project outcomes.

To this purpose different parallel dissemination options have been exploited and related actions performed.
DSPACE Logo (Figure FR 11) has been selected in order to provide a one-shot simple visual attractive item in line with project development aims.
The concept at the base of Logo creation is the following.

The Year 2011 was the starting year of DSPACE Project and is also the ending year for American Space Shuttle missions. On 21th July of this year the last launch for this spacecraft has been performed. The use of Space Shuttle on DSPACE Logo has two main aims:
• A tribute to Space exploration human activity. Space Shuttle is an important Spacecraft that has been for about thirty years the symbol of human activity in Space
• A reminder of DSPACE Project main aim: Europe Space “Independence” and “Non Dependence”. On the other side, Space Shuttle has been also the symbol of American leadership and supremacy in Space domain. The association of this spacecraft image to the ending year of its activities on DSPACE Logo communicates the end of a Space age in which Space balance of power system has been focused on American technology, and the will to build a new space age in which Europe shall have the internal self-contained resources for being a leading actor.

The Logo has been created using the “LSM Remembering SS Columbia” font from London’s Letters Website ( which owner gently granted its free usage for the creation of the DSPACE Project Logo and for DSPACE Project activities in general.
The DSPACE Public Website is another important external (but also internal) communication mean. The DSPACE website serves as a primary source for exposure. This space acts as a communication tool to aid the dissemination of DSPACE initiatives in order to aggregate as much consensus and awareness as possible. For this reason, a complete set of information and communication services are made available to website visitors at following domain:
The website offers information concerning relevant events, as well as demonstrates project results and project potentialities to the widest audience. It is divided in a public and a private section (restricted to project partners).
Detailed description of Project Website and features are provided in following dedicated section.

DSPACE Consortium partners took part to different events, public relations, publications and produced dissemination material to be distributed in order to continuously promote project activities and outcomes. Here below an overview of the main dissemination activities produced during DSPACE Project is provided:
• July 2011 - DSPACE activity has been inserted in “A European Journey - Space Research projects under the 7FP for Research” publication. Download of electronic format of the whole document is available at DSPACE brochure is in "Developing Critical Technologies" section (pag. 138).
"A European Journey" is the fourth in a series of European Commission brochures featuring EU Space Research projects. The first edition, "Space Research – Developing applications for the benefit of the citizens", reviews FP6 projects, whilst the second edition, "Let’s embrace space – Space Research projects under the 7th Framework Programme for Research", is devoted to projects from the 1st FP7 space call. "Desire for space" features project from the 2nd FP7 space call.
• September 2011 - DSPACE activity has been introduced during the “Technology Harmonisation Advisory Group” (THAG) meeting held at European Space Research and Technology Centre (ESTEC) in Noordwijk (Netherlands).
Technology Harmonisation Advisory Group (THAG) has been created in 2005 by European Space Agency’s as main mean to exploit the Agency Executive’s European Space Technology Harmonisation process. This activity aims at involving all actors and ad-hoc experts in related areas in order to discuss various technologies and share information among the stakeholders with the scope of agreeing on Europe wide roadmaps recommending technological developments to fulfil the objectives set at European level.
• September 2011 - Aerospace and Defence Industries Association of Europe (ASD) introduced short overview on DSPACE activity during the ESA/EDA/EU Mapping Meeting on Critical Technologies for Non-Dependence held at European Space Research and Technology Centre (ESTEC) in Noordwijk (Netherlands)
The European Commission (EC), the European Space Agency (ESA) and the European Defence Agency (EDA), together with European stakeholders conduct actual European Non-Dependence process for the identification of the urgent actions for Critical Space Technologies. The Mapping Meeting objective is to take stock of the actions implemented over previous two years and gather feedback from Member States and Industry, in order to refine the European approach to Non-Dependence issue.
• October 2011 - Article named "FP7 DSPACE Project: A New Digital Signal Processor for Space Applications" describing DSPACE project activities has been published on number 28th of HiPEAC newsletter (October 2011).
European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) is an open network which mission is to steer and increase the European research in the area of high-performance and embedded computing systems. Newsletter is a quarterly publication providing the latest news on the activities within the European HiPEAC network sent to more than 500 researchers from academia and industry, and company managers in Europe, America and Asia.
• May 2012 - Overview on DSPACE project has been introduced during DASIA Eurospace conference in Dubrovnik (Croatia).
Eurospace is the trade association of the European Space Industry. It is a non-profit European organisation created in 1961. Eurospace member companies today represent 90% of the total turnover of the European Space Industry. Eurospace fosters the development of space activities in Europe and promotes a better understanding of space industry related issues and problems. Data Systems in Aerospace (DASIA) conference is dedicated to information technologies issue in space applications context.
• May 2012 - Overview on DSPACE project activities has been presented during ASI 7th Framework Programme Workshop on Space Foundations in Rome (Italy).
The Italian Space Agency (Agenzia Spaziale Italiana, ASI) was founded in 1988. Its purpose was to coordinate all of Italy's efforts and investments in the space sector that had begun in the 1960s. Within twenty years' time, ASI became one of the most significant players in the world in space science, satellite technologies and the development of mobile systems for exploring the Universe. Today, ASI has a key role at the European level where Italy is the third contributor country to the European Space Agency.
• June 2012 - DSPACE project activity has been overviewed at 44th GE (Associazione Gruppo Italiano di Elettronica, Italian Group of Electronics Association) conference in Marina di Carrara (Tuscany,IT).
Italian Group of Electronics Association, founded in 2011, is a non-profit association whose aims are the promotion, development and dissemination of knowledge of training, research and technological transfer within the electronics industry. DSPACE project activity has been overviewed during the 44th annual meeting of members of the association taking advantage of a high level expertise audience in electronic research and industrial field.
• July 2012 - In “Design Technologies for Wireless multiprocessor Systems-on-Chip” Doctor of Philosophy student course held by Prof. Rainer Leupers (RWTH Aachen University), in Engineering Information Technology Department of Pisa University (Italy) details related to DSPACE activities have been presented
The University of Pisa (Italian Università di Pisa), is a public university in Pisa, Italy. It is one of the oldest universities in the country. It was officially founded on September 3, 1343 by an edict of Pope Clement VI, although there had been lectures on law in Pisa since the 11th century. Engineering Information Technology Department is involved in deep research activities on many fields related to Electronics, Informatics and Telecommunications.
• August 2012 - DSPACE project activities have been presented during ESA DSP Day in ESTEC (Netherlands) organised by ESA On-Board Payload Data Processing Section.
European Space Agency's On-Board Payload Data Processing Section as part of ESA’s Directorate of Technical and Quality Management, provides technical support in the areas of competence to all programme directorates in order to support their missions and developments. On the other side, the section is responsible for initiation and execution of technology developments that may lay the foundation for future missions.
ESA DSP day was an important meeting organised at ESTEC premises in order to take the stock of the situation on main parallel developments carried on in different activities promoted by ESA for targeting the new high performances European space DSP.
• October 2012 - DSPACE project activity has been overviewed at ESTEL conference in Rome (Italy). Related documentation is available at
ESTEL Conference is the first international IEEE-AESS conference in Europe dedicated to telecommunications via satellite for “Advanced Services and Applications, Architectures, Technologies and Terminals”. The meeting welcomes the most important international experts in the sectors of satellite communications, antennas, navigation systems, integrated satellite systems, sensing and electronic systems engineering, emerging technologies and relative Value added Services & Applications.
• November 2012 - DSPACE project activity has been presented at second FP7 space conference in Larnaca (Cyprus).
Conference presents the results of the FP7 Space Research Programme and investigates related future options for European space research. The 2nd FP7 Space Conference gathered around 200 participants: space experts, researchers and industry stakeholders, personalities from European and international space science and research organisations, coordinators and members of FP7 funded research projects, representatives of national space administrations and space agencies, high level EC and ESA officials
• February 2013 - Article on DSPACE activity has been published on 2nd volume of "Let's Embrace Space 2012" publication. Book is free downloadable on EU Bookshop website. Chapter 37 (pages from 386 to 393) is dedicated to DSPACE.
"Let's Embrace Space" book is a publication of European Commission's Directorate-General for Enterprise and Industry that has the mission to promote a growth-friendly framework for European enterprises. The second volume of the publication presents, in a concise and illustrative way, the results of 55 projects funded under the EU Space Research Programme. Book free download is available at
• February 2013 - DSPACE activity has been presented during "Real-Time Image and Video Processing 2013 SPIE Conference" in Burlingame (California, United States). Information on DSPACE has been inserted also in "Newsroom" section of SPIE website.
SPIE, the international society for optics and photonics, was founded in 1955 to advance light-based technologies. Serving more than 225,600 constituents from 150 countries, SPIE advances emerging technologies through interdisciplinary information exchange, continuing education, publications, patent precedent, and career and professional growth. SPIE annually organizes and sponsors around 25 major technical forums, exhibitions, educational programs in America, Europe, Asia and South Pacific.
• March 2013 - DSPACE activity has been presented during "APPLEPIES 2013" Conference held in Rome (Italy) at "La Sapienza" University premises.
The 2013 International Conference on Electronics Application (APPLEPIES 2013) has been organised by the University of Rome, La Sapienza, on 7–8/03/2013 to confront industrial & research activities in the field of Electronics Applications. In particular, authors submitted and overviewed papers describing original researches about: Information Communication Technology; Biotechnology; Space; Secure, clean and efficient energy; Environment; Smart, green and integrated transport (
• July 2013 - Article on DSPACE has been published on 24th volume of "research*eu results magazine" publication. Book is free-downloadable on EU Bookshop website. Section "Processing and compressing space data" (page 39) is dedicated to DSPACE.
"research*eu results magazine" is a publication of the Publications Office of the European Union featuring highlights from the most exciting EU-funded research and development projects. It is published 10 times per year in English, and covers: Biology and medicine, Social sciences and humanities, Energy and transport, Environment and society, IT and telecommunications, Industrial technologies and Space. Magazine free download is available at
• September 2013 - Article on DSPACE activity submitted to APPLEPIES 2013 conference has been selected for being published on "Lecture Notes in Electrical Engineering" Journal (Springer). Publication procedure is regularly in progress.
"Lecture Notes in Electrical Engineering" (LNEE) is a book series of Springer publishing house which reports the latest research and developments in Electrical Engineering. The audience for the books in LNEE consists of advanced level students, researchers, and industry professionals working at the forefront of their fields. Much like Springer’s other Lecture Notes series, LNEE is distributed through Springer’s print and electronic publishing channels.
All above listed information is available on DSPACE Project Website together with related details and material overview.
On the Project Website it is possible to download also the electronic copy of the DSPACE Brochure (Figure FR 12) developed in order to provide a one-shot single paper overview of main project outcomes.
Document highlights the context of the project, the delivered outputs (with a focus on both SW and HW products) and the performances provided by DSPACE system. 50 paper copies of DSPACE Brochure have been printed at the end of the activity in order to be distributed at main relevant related dissemination events.
DSPACE project description is available also on "Embrace Space" smartphone application. The "Embrace Space" Space Research application is the first EU-funded FP7 initiative that allows the user to discover the FP7 Space projects in one convenient and easy-to-use mobile application. The contents are labelled under 3 themes: International Space Station (ISS), Earth and Space. Aware of the importance of mobile channel as valid complement in promoting and informing on DSPACE activity, project consortium started the procedure in order to update application database with project outcomes in order to leave also in this dissemination context clear and out of date information on activity performed. “Embrace Space” application is available for both IOS and Android operating systems and it is possible to download it for free following EC promotional link ( or directly from online market stores.
All dissemination materials related to DSPACE activity have been produced respecting all communications standards of Grant Agreement provisions and REA and EC recommendations (i.e. “Guidance Notes on Project Reporting” reference document, June 2010).
The Exploitation of DSPACE results has been carried out on the base of feedbacks and guidelines produced by mentioned dissemination activities but also by means of a constant investigation on the related space DSP market in order to monitor developed device appeal, to contextualise its opportunities and to reasonably depict and select available business models.

In this context DSPACE original aim is to contribute to create the necessary concepts and technological solutions to establish a platform for the new generation of DSPs in space applications for an independent European technological environment. DSPACE actually competes with mentioned possible future options for the next generation of European DSPs under investigation by ESA.
In this context, DSPACE represents an additional possibility for Europe players to reduce their dependence on critical technologies and capabilities from outside for the future space applications and DSPACE original development aim is in line with last mentioned approach because targets stand-alone, mature and reliable DSP.
However, the analysis of DSP space market needs and the beta testing investigation performed during project activity by means of survey sharing and direct contacts with main space actors in order to collect feedbacks on developed device market appeal and evaluation, underlined DSPACE issues linked to its R&D nature and recent development life that seems to put it aside from short time space commercialisation.
The gap between actual development status (however estimated as commendable in relation to available time and resources) and maturity level requested for a candidate DSP to trigger space main actors interest in its space porting is high in terms of effort and costs needed. Therefore in this scenario DSPACE could only be taken as a back-up solution for ESA in Next Generation DSP pursuit, if actual negotiation for purchasing Analog Devices ADI 21469 IP licence will not succeed.
However DSPACE solution can rely on the control of IP Core and the innovative design approach representing its main strong points respect to other concurrent solutions and allowing successful device placement on space market to be not totally kept out but maybe simply postponed. In the meantime a reasonable approach in order to raise reliability and maturity level of DSPACE Core has been individuated in the exploitation of its good opportunities in R&D field. DSPACE IP Core diffusion could allow research and academic entities to produce development activities on it, raising its knowledge, usage refinement and maturity level and allowing in a second time possible space business development along the lines of LEON device experience.
Therefore main channel of exploitation activity has been individuated in the web sharing for research purposes suggested by ESA reviewer during first annual review meeting and adopted by Project Consortium as final approach for allowing future DSPACE business.

Within the end of 2013 DSPACE IP will be available on Design and Reuse portal ( ?providing external audience with a package containing following items:
2) C Compiler
3) Binary Tools
4) Instruction Set Simulator
5) DSPACE SDE and benchmarks set
6) Descriptive/Instructions distribution documentation

Legal/Usage approach options for available items will be the following:
• Pure academic research purposes: free availability of previous items 1), 2), 3), 4), 5), 6). Item 7) is composed by RTL generated by LISA model and a complementary VHDL. RTL generation is not open source and needs Synopsys Processor Designer (PD) license available at nominal charge via Europractice. Users owning PD license will be provided free with complementary VHDL in order to exploit whole DSP features.
• Commercial use: negotiate licensing for all items with the relevant DSPACE consortium partners case by case. PD license to be purchased from Synopsys.
DSPACE Demo Board ordering, allowing users to produce demonstrator-based refinement activities on DSPACE, will be offered as additional option to be negotiated directly with SITAEL S.p.A.
DSPACE package will be free distributed to the end user only after his signature of a disclaimer legally obligating him to its non-commercial purposes usage.
In relation to web-sharing approach DSPACE future will mainly depend on the clear intention and plan of the partners to implement the results in their own business practices by means of their ability to inform and involve potential external users, research and academic entities to produce development activities on it, raising its knowledge, usage refinement and maturity level.

On this side, it is expected that the results of the project will influence a wide community of researchers, developers and users at national, European, and international levels.
On the other side, intention and plan of the partners to continue promoting and maintaining DSPACE appeal through the main space players (National Space Agencies, ESA and potential external users) will define possible future DSP chances to remain an appetible/meaningful backup option in European next generation space DSP pursuit.
Anyway, outputs of DSPACE activity are expected to impact and produce future contribution on reduction of dependency on critical and importation-restricted technologies and on increase of European components usage in future space applications enhancing the worldwide technical competitiveness of European satellites vendors and opening new competition opportunities for European manufacturers and new collaborations between European non-space and space industries and projects. It is expected also the results of the project to influence a wide community not only limited to space market but also including equipment manufacturers, software developers, system integrators, research and development, academia.

List of Websites:
The public project website ( is on-line starting from August 2011. It plays a fundamental role in creating synergies between the other dissemination and communication channels activated by the project and enables to collect and share information among the consortium partners as well as to present project results and public dissemination material to the widest worldwide community.

The web site architecture has been designed in order to satisfy the requirements of two different kinds of users: participants to the project and general public users. The website grants two different levels of accessibility:
• The public pages of website are directed to a general audience that wants to know more about the DSPACE project. A general description of the project along with its goal, the established development consortium with the main contacts and the public dissemination materials and results can be found browsing this part of the website.
• The private pages (restricted area) represent a repository for the project documents to facilitate discussion among partners and general project management. All restricted project documents (technical and financial reports, deliverables and internal documentation) uploaded in this section are available for consultation and download only for the consortium’s members via a log in procedure.

The contents of both public and private areas have been regularly updated during the project life and are at present up to date with outcomes produced at the time of project activity completion. All website pages are developed in English language and clearly refer to FP7 project context and funding according to related Grant Agreement provisions.

The public area of the website consists of the following pages:
• Home page: provides a general description of the activities and motivations related to the DSPACE project (Figure FR 13)
• Objectives page: presents the final objectives and goals to be accomplished in the project (Figure FR 14)
• Consortium page: describes the consortium established for the development of the DSPACE project. For each partner the company name is shown along with the company logo and a direct link to its own website. A nice photo of all participants to the DSPACE kick-off meeting completes the page (Figure FR 15)
• Contacts page: provides for each partner the contact of the person in charge of coordinating the activity to be performed by its company in the framework of the DSPACE project (Figure FR 16)
• Dissemination page: makes available for consulting and downloading all dissemination material developed during the life of the project. All users can access this material, but only the people that have a log in account can upload materials in this area (Figure FR 17).
• News Page: accessible by means of clicking on the blue box on the right of each page in which main news on DSPACE are scrolling, it provides the details of the listed past/upcoming tracked events related to DSPACE (Figure FR 18)

The restricted area includes only one page:
• Private area: accessible only after a successful log in procedure based on username and password recognition. There are three main areas, dedicated to management, technical topics and project news respectively. All valid users can upload and download materials in this area during the life of the project. The hierarchy of the management folder allows to provide all members of the consortium with the minutes of the meeting, the general Gantt, reports and deliverables, templates and other documents or information related to the management of the project. The structure of the technical folder reflects the work plan of the project and the work-packages fragmentation. Deliverables, internal technical notes and other useful material are hosted in this part. (Figure FR 19)

Each page of the website has a fixed structure composed by three main columns. The left column includes, from top to bottom respectively:
• The logo of the project
• The navigation bar to switch among all pages
• The box for the log in procedure to access the private area of the website
• The logo of FP7 Program
The right portion represents the main information content of the page, allowing in some cases to interact with the website (i.e. for upload or download materials). Depending on the page considered, this part looks like a text, a table or a list.
On the right column, the box containing the scrolling list of main news on DSPACE is housed.

The lower bar of each page reports:
• EU flag
• Information on project EU funding program
• Number of project EU Grant Agreement.

Here below the list of relevant contacts related to DSPACE project is provided:
• SITAEL S.p.A. (Coordinator Partner,,
o Responsible Contact: Ms. Annamaria Colonna (Project Coordinator, tel.: +39 050 9912116, mail:
• INTECS S.p.A. (,
o Responsible Contact: Mr. Alessandro Brachini (tel.: +39 050 9657506, mail:
• Dept. of Information Engineering - University of Pisa (,
o Responsible Contact: Prof. Luca Fanucci (tel.: +39 050 2217668, mail:
• Space Applications Services NV (,
o Responsible Contact: Mr. Richard Aked (tel.: +32 2 721 54 84, mail:
• Rheinisch-Westfaelische Technische Hochschule Aachen (,
o Responsible Contact: Prof. Rainer Leupers (tel.: +49 241 80 28301, mail:

Short overview on DSPACE project is also available in following sections of some of project partners websites:

Related information

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