Final Report Summary - ATWC (Adaptive Transceivers for Wireless Communications)
Project Summary
The project uses adaptive optimization of wireless terminals to reduce carbon emission and battery disposal while allowing broadband connection any time in any place The main innovation is dynamic re-configuration to match the changing environment thereby meeting Quality of Service (QoS) with minimum energy consumption. Achieving this goal demands significant progress in terminal re-configurability and estimation of its operating conditions involving skills in electronic and communication. The research concentrates on the analog/RF portion of the transceiver with the partners focus different areas: Universities of Pavia and Lund on RF circuit, Marvell on definition of the industrial targets, Ericsson on communications and system aspects.
Project Overview
While information and communication technology (ICT) has helped reduce pollution, the communication network keeps increasing its energy dissipation. Since cellular networks uses 0,33% of the global electricity consumption and increases by 10x every 5 years, future wireless terminals should use less energy to reduce their environmental impact. Energy efficiency is impaired by limitations in terminal adaptability and in the knowledge of the communication channel. The project aims at using re-configurability to achieve minimum energy consumption for a given QoS. The project applies “Cross-layer reconfiguration” (CLO) to dynamically and autonomously adapt the mobile terminals to the environment represented by the three scenarios (with corresponding receiver power consumption) shown in Fig. 1. As opposed to previous implementations the analog/RF front-end is reconfigurable and provides information on the channel, to the controlling algorithm.
Operating condition extraction and adaptive optimization are done both at analog and digital level. Extra area and power to monitor, to process the extracted information and to add reconfiguration is minimized to make the new approach advantageous. To implement an adaptive receiver requires multiple skills. The teams have expertise in integrated circuit, communications systems and industrial targets. Adaptive optimization will be compared to the “worst case scenario” approach, the building blocks (RX, TX and frequency synthesis) will be designed, the algorithms that oversee reconfiguration will be studied and the results will be disseminated through internal workshops and through publication at international conferences and journals.
Work performed
The activities performed followed the planned time schedule in a resalable way and the initial delay was fully recovered. The project was divided in six WP covering different research aspects that needed to implement a reconfigurable terminal. WP1 focused on the overall system including definition of the requirements for the terminal (task 1.1) and of the optimization and reconfiguration strategy (task 1.2). Task 1.1 was achieved early in the project. The requirements where defined for both RX and TX. The downlink was studied using 3GPP pre-defined test cases whose combination provides a good overview of the performance required by the blocks. The uplink was evaluated according to specific metrics such as EVM and ACLR to highlight potential challenges not visible at block level. Specification where defined for the circuit WPs. Task 1.2 was completed with some delay but this did not affected the other WPs. The optimization and reconfiguration strategy was defined through a set of four possible scenarios that extends those given by 3GPP for the down-link as shown in Fig. 2, and for each scenario a 3GPP test case set was applied to the receiver.
Adaptation was limited to RX since in TX it is already performed by the base station. The main result was to define the possibility of adapting the system within a packet of data to avoid specific time slot dedicated to adaptation. The circuit design work packages, where all planned for the second half of the project. After the initial delay, the project had an acceleration that produced important results on circuit design/implementation earlier than planned. For WP2 (RX) both Task 2.1 (on the RF portion) and Task 2.1 (on the analog base-band) where fully achieved. An architecture for a reconfigurable multi-standard receiver based on a filtering ADC after the down converter was proposed. Several receivers were designed i.e. two without any off chip filtering (SAW-less), a duplexer less, a single ended inductor less and a differential with current reuse. For WP3 (TX) both Task 3.1 (on to the RF portion) and Task 3.1 (on the base-band) where fully achieved. Three progressively more efficient multi-standard transmitters were designed. They use a class A/B up-converter to reduce power consumption and out of band noise emission with the goal to eliminate external SAW filters. For WP4 (frequency synthesis) Task 4.1 (PLL) was achieved beyond the plan. Several Voltage Controlled Oscillators (VCO) were designed including reconfigurable, class B with tail filter, class C, class D and hybrid class C/class B. A simplified analysis suitable for benchmarking VCO was performed. Finally an All Digital PLL was implemented together with a new TDC. Task 4.2 (LO distribution) was carried on internally by Marvell and was achieved but not disseminated. For WP5 (Prototyping), several circuits (three TX chains, four RX chains, 6 VCOs a PLL etc). were completed on a time scale that was significant ahead of schedule. Technology access was provided by Marvell in 55 and 28 nm standard CMOS and by STM in 55nm in SOI-CMOS (the latter not foreseen in the plan. Finally for WP6 (Management and Dissemination) a Consortium Agreement was signed, three internal and one external international workshops and several meeting were organized and many publications presented in international conferences or scientific magazines.
Achieved results
The results of the project are twofold i.e. the researchers seconded or hired and the milestones reached and the deliverable produced especially the fabricated prototypes and scientific publications. A successful plan to recover the initial delay was implemented. With respect to the first point the situation is as follows: 94 months of secondments and 48 months of recruitments were implemented versus 96 and 48 respectively planned. With respect to the second point, all milestone and deliverable were achieved. The key results are. For WP1, the definition of the specifications for the building blocks of the terminal and the definition of the optimization strategy. This did not produce publications but was crucial for the success of the entire project. For WP2, the proposal of a more digital RX architecture and its simulation, the realization on silicon of two RX chain capable to work without an input SAW filters and the submission for fabrication of a Duplexer-less and of an inductor less single ended transceiver. For WP3, the realization on silicon of two very efficient TX chain (far all standards including LTE) intended for SAW less operation and the submission for fabrication of a further optimized. For WP4, the realization on silicon of 6 optimized VCOs including one reconfigurable in performance without efficiency penalty. For WP5 the integration of 11 chips in 55/40nm CMOS technology from Marvell and 55nm SOI-COMS from STM (the second not foreseen in the plan) and the submission for fabrication of 4 chips in 55/28nm CMOS from Marvell. For WP6, the implementation of the WEB page of the project http://www-3.unipv.it/microlab/mariecurie and the production of more than 20 international publications including 5 at the most important magazine in the field the IEEE Journal of Solid State Circuits and 6 at the most important conference in the filed the International Solid State Circuit Conference.
Expected impact
The ultimate goal of the project is to make available to the market a more energy efficient wireless terminal leveraging the concept of cross layer optimization. Although the success of such a plan requires multiple progress in diverse areas that cannot be fully addressed in a project like this, we have demonstrated the feasibility of some key building blocks. This may help motivating the start of research in other complementary areas. In general a more efficient terminal can have significant impact toward the goal of a more eco-friendly communication infrastructure. Furthermore, the exploitation of the results will benefit the industrial partners in terms competitive advantages in the market. Finally it is expect that the experience acquired by the seconded researchers will extend their technical background and their ability to relate to new environments.
The project uses adaptive optimization of wireless terminals to reduce carbon emission and battery disposal while allowing broadband connection any time in any place The main innovation is dynamic re-configuration to match the changing environment thereby meeting Quality of Service (QoS) with minimum energy consumption. Achieving this goal demands significant progress in terminal re-configurability and estimation of its operating conditions involving skills in electronic and communication. The research concentrates on the analog/RF portion of the transceiver with the partners focus different areas: Universities of Pavia and Lund on RF circuit, Marvell on definition of the industrial targets, Ericsson on communications and system aspects.
Project Overview
While information and communication technology (ICT) has helped reduce pollution, the communication network keeps increasing its energy dissipation. Since cellular networks uses 0,33% of the global electricity consumption and increases by 10x every 5 years, future wireless terminals should use less energy to reduce their environmental impact. Energy efficiency is impaired by limitations in terminal adaptability and in the knowledge of the communication channel. The project aims at using re-configurability to achieve minimum energy consumption for a given QoS. The project applies “Cross-layer reconfiguration” (CLO) to dynamically and autonomously adapt the mobile terminals to the environment represented by the three scenarios (with corresponding receiver power consumption) shown in Fig. 1. As opposed to previous implementations the analog/RF front-end is reconfigurable and provides information on the channel, to the controlling algorithm.
Operating condition extraction and adaptive optimization are done both at analog and digital level. Extra area and power to monitor, to process the extracted information and to add reconfiguration is minimized to make the new approach advantageous. To implement an adaptive receiver requires multiple skills. The teams have expertise in integrated circuit, communications systems and industrial targets. Adaptive optimization will be compared to the “worst case scenario” approach, the building blocks (RX, TX and frequency synthesis) will be designed, the algorithms that oversee reconfiguration will be studied and the results will be disseminated through internal workshops and through publication at international conferences and journals.
Work performed
The activities performed followed the planned time schedule in a resalable way and the initial delay was fully recovered. The project was divided in six WP covering different research aspects that needed to implement a reconfigurable terminal. WP1 focused on the overall system including definition of the requirements for the terminal (task 1.1) and of the optimization and reconfiguration strategy (task 1.2). Task 1.1 was achieved early in the project. The requirements where defined for both RX and TX. The downlink was studied using 3GPP pre-defined test cases whose combination provides a good overview of the performance required by the blocks. The uplink was evaluated according to specific metrics such as EVM and ACLR to highlight potential challenges not visible at block level. Specification where defined for the circuit WPs. Task 1.2 was completed with some delay but this did not affected the other WPs. The optimization and reconfiguration strategy was defined through a set of four possible scenarios that extends those given by 3GPP for the down-link as shown in Fig. 2, and for each scenario a 3GPP test case set was applied to the receiver.
Adaptation was limited to RX since in TX it is already performed by the base station. The main result was to define the possibility of adapting the system within a packet of data to avoid specific time slot dedicated to adaptation. The circuit design work packages, where all planned for the second half of the project. After the initial delay, the project had an acceleration that produced important results on circuit design/implementation earlier than planned. For WP2 (RX) both Task 2.1 (on the RF portion) and Task 2.1 (on the analog base-band) where fully achieved. An architecture for a reconfigurable multi-standard receiver based on a filtering ADC after the down converter was proposed. Several receivers were designed i.e. two without any off chip filtering (SAW-less), a duplexer less, a single ended inductor less and a differential with current reuse. For WP3 (TX) both Task 3.1 (on to the RF portion) and Task 3.1 (on the base-band) where fully achieved. Three progressively more efficient multi-standard transmitters were designed. They use a class A/B up-converter to reduce power consumption and out of band noise emission with the goal to eliminate external SAW filters. For WP4 (frequency synthesis) Task 4.1 (PLL) was achieved beyond the plan. Several Voltage Controlled Oscillators (VCO) were designed including reconfigurable, class B with tail filter, class C, class D and hybrid class C/class B. A simplified analysis suitable for benchmarking VCO was performed. Finally an All Digital PLL was implemented together with a new TDC. Task 4.2 (LO distribution) was carried on internally by Marvell and was achieved but not disseminated. For WP5 (Prototyping), several circuits (three TX chains, four RX chains, 6 VCOs a PLL etc). were completed on a time scale that was significant ahead of schedule. Technology access was provided by Marvell in 55 and 28 nm standard CMOS and by STM in 55nm in SOI-CMOS (the latter not foreseen in the plan. Finally for WP6 (Management and Dissemination) a Consortium Agreement was signed, three internal and one external international workshops and several meeting were organized and many publications presented in international conferences or scientific magazines.
Achieved results
The results of the project are twofold i.e. the researchers seconded or hired and the milestones reached and the deliverable produced especially the fabricated prototypes and scientific publications. A successful plan to recover the initial delay was implemented. With respect to the first point the situation is as follows: 94 months of secondments and 48 months of recruitments were implemented versus 96 and 48 respectively planned. With respect to the second point, all milestone and deliverable were achieved. The key results are. For WP1, the definition of the specifications for the building blocks of the terminal and the definition of the optimization strategy. This did not produce publications but was crucial for the success of the entire project. For WP2, the proposal of a more digital RX architecture and its simulation, the realization on silicon of two RX chain capable to work without an input SAW filters and the submission for fabrication of a Duplexer-less and of an inductor less single ended transceiver. For WP3, the realization on silicon of two very efficient TX chain (far all standards including LTE) intended for SAW less operation and the submission for fabrication of a further optimized. For WP4, the realization on silicon of 6 optimized VCOs including one reconfigurable in performance without efficiency penalty. For WP5 the integration of 11 chips in 55/40nm CMOS technology from Marvell and 55nm SOI-COMS from STM (the second not foreseen in the plan) and the submission for fabrication of 4 chips in 55/28nm CMOS from Marvell. For WP6, the implementation of the WEB page of the project http://www-3.unipv.it/microlab/mariecurie and the production of more than 20 international publications including 5 at the most important magazine in the field the IEEE Journal of Solid State Circuits and 6 at the most important conference in the filed the International Solid State Circuit Conference.
Expected impact
The ultimate goal of the project is to make available to the market a more energy efficient wireless terminal leveraging the concept of cross layer optimization. Although the success of such a plan requires multiple progress in diverse areas that cannot be fully addressed in a project like this, we have demonstrated the feasibility of some key building blocks. This may help motivating the start of research in other complementary areas. In general a more efficient terminal can have significant impact toward the goal of a more eco-friendly communication infrastructure. Furthermore, the exploitation of the results will benefit the industrial partners in terms competitive advantages in the market. Finally it is expect that the experience acquired by the seconded researchers will extend their technical background and their ability to relate to new environments.