Final Report Summary - WISE (Nanowire Structures for Energy Conversion)
The aim of the project was to develop materials for efficient thermo-electric energy conversion. A thermoelectric energy converter (TEC) turns heat directly into electrical energy without the need for any engine or moving parts and without emitting any harmful greenhouse gas. Current TECs are expensive and inefficient and therefore their use is confined to some niche applications. With a significant improvement of thermoelectric materials with respect to the current state of the art a number of applications will open up.
Recent theoretical simulations and experimental results have shown that III-V semiconductor nanowires can serve as efficient thermoelectric materials, owing to their lower thermal conductivity and high carrier mobility. The project therefore had two main objectives. First, the investigation of homogeneous III-V nanowires for their use as thermoelectric material. This comprises the development and investigation of catalyzed and non-catalyzed growth of homogenous III-V nanowires on silicon and their subsequent morphological, structural and thermoelectric characterization. The second objective was the investigation of nanowire heterostructures using optimized materials from Objective 1. This objective aimed at the growth and characterization of axial A/B-heterostructure nanowires and A/B/A structures for evaluation of periodic material modulation.
The research pursued in WISE explored and developed III-V semiconductor nanowires and heterostructures to be used as an efficient thermoelectric material. The project comprises the growth of III-V semiconducting nanowires using the metal organic chemical vapour deposition (MOCVD), structural and morphological characterization of the nanowire material and detailed characterization of the electrical and thermal properties for thermoelectric applications.
The material system investigated was InxGa1-xAs grown by various techniques directly on Si. The techniques employed were the vapour liquid solid growth using Au as catalyst, non-catalytic growth using e-beam patterned oxide hole masks and non-catalytic growth on very thin native oxide. Furthermore, a new technique of selective growth of nanowires within nanotube templates was successfully demonstrated. Growth parameters were optimized in order to achieve high quality nanowires and heterostructures, get control of nanowire diameter, length, ternary composition and conductivity.
A highlight of the growth results is the demonstration of catalyst-free growth technique to directly integrate III–V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. Single-crystalline InAs, GaAs and InGaAs wires on Si as well as InAs–InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5–6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core–shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III–V based electronic, optoelectronic and thermoelectric devices on silicon.
A full characterization of the electrical as well as thermal transport properties of the InAs nanowires was performed. For measuring the thermal transport two methods were applied the self-heating method and a MEMS device. Using self-heating method, InAs NWs with diameter of 100 nm and resistivities of ca 25 mOhm cm at room temperature were measured. Thermal conductivity of k = 1.8 W/(m K) was obtained, which is about 20 to 30 times smaller than in bulk InAs demonstrating the potential of nanowires for thermoelectric applications.
The novel growth technique developed in this project is considered a highly attractive way to integrate III-V materials on a Si platform. It has potential to have significant impact in monolithic integration of III-V semiconductors with silicon which is of high interest to the semiconductor industry for various applications. The roadmap of future semiconductor electronic devices foresees the introduction of III-V materials as active channel in field-effect transistors in order to achieve continued performance increase. Furthermore the technique demonstrated could enable the direct integration of III-V optoelectronic devices directly on silicon.
The thermoelectrical characterization of InAs nanowires demonstrated their potential for thermoelectrical applications. In particular a low thermal conductivity value was measured for the InAs nanowires compared to bulk material which demonstrates the potential of one-dimensional structures for use as a thermoelectric material.
Recent theoretical simulations and experimental results have shown that III-V semiconductor nanowires can serve as efficient thermoelectric materials, owing to their lower thermal conductivity and high carrier mobility. The project therefore had two main objectives. First, the investigation of homogeneous III-V nanowires for their use as thermoelectric material. This comprises the development and investigation of catalyzed and non-catalyzed growth of homogenous III-V nanowires on silicon and their subsequent morphological, structural and thermoelectric characterization. The second objective was the investigation of nanowire heterostructures using optimized materials from Objective 1. This objective aimed at the growth and characterization of axial A/B-heterostructure nanowires and A/B/A structures for evaluation of periodic material modulation.
The research pursued in WISE explored and developed III-V semiconductor nanowires and heterostructures to be used as an efficient thermoelectric material. The project comprises the growth of III-V semiconducting nanowires using the metal organic chemical vapour deposition (MOCVD), structural and morphological characterization of the nanowire material and detailed characterization of the electrical and thermal properties for thermoelectric applications.
The material system investigated was InxGa1-xAs grown by various techniques directly on Si. The techniques employed were the vapour liquid solid growth using Au as catalyst, non-catalytic growth using e-beam patterned oxide hole masks and non-catalytic growth on very thin native oxide. Furthermore, a new technique of selective growth of nanowires within nanotube templates was successfully demonstrated. Growth parameters were optimized in order to achieve high quality nanowires and heterostructures, get control of nanowire diameter, length, ternary composition and conductivity.
A highlight of the growth results is the demonstration of catalyst-free growth technique to directly integrate III–V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. Single-crystalline InAs, GaAs and InGaAs wires on Si as well as InAs–InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5–6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core–shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III–V based electronic, optoelectronic and thermoelectric devices on silicon.
A full characterization of the electrical as well as thermal transport properties of the InAs nanowires was performed. For measuring the thermal transport two methods were applied the self-heating method and a MEMS device. Using self-heating method, InAs NWs with diameter of 100 nm and resistivities of ca 25 mOhm cm at room temperature were measured. Thermal conductivity of k = 1.8 W/(m K) was obtained, which is about 20 to 30 times smaller than in bulk InAs demonstrating the potential of nanowires for thermoelectric applications.
The novel growth technique developed in this project is considered a highly attractive way to integrate III-V materials on a Si platform. It has potential to have significant impact in monolithic integration of III-V semiconductors with silicon which is of high interest to the semiconductor industry for various applications. The roadmap of future semiconductor electronic devices foresees the introduction of III-V materials as active channel in field-effect transistors in order to achieve continued performance increase. Furthermore the technique demonstrated could enable the direct integration of III-V optoelectronic devices directly on silicon.
The thermoelectrical characterization of InAs nanowires demonstrated their potential for thermoelectrical applications. In particular a low thermal conductivity value was measured for the InAs nanowires compared to bulk material which demonstrates the potential of one-dimensional structures for use as a thermoelectric material.