HARDWARE ENABLED CRYPTO AND RANDOMNESS

Resultado final

Report on the Security Evaluation of Cryptographic Algorithms and Countermeasures when non Ideal Hardware Building Blocks are Used

This report is output of T3.1 and T3.2.

Demonstrator Specification

This deliverable will contain detailed Software & hardware specifications of the demonstrator platform and the hector hardware device as output of T4.1.

Report on the Efficient Implementations of Crypto Algorithms and Building Blocks and on Cost and Benefits of Countermeasures Against Physical Attacks

This report is output of T3.3. and T3.4

Report on Attacks

This report will present and analyse results of selected attacks, including side-channel attacks (power, time, EM), fault attacks (glitches, power supply variation, temperature variations), EM perturbation attacks and others.

Data Management Plan (DMP)

As HECTOR is taking part in the Pilot on Open Research Data a first version of the DMP as an early deliverable will be provided within the first six months of the project The purpose of the DMP is to provide an analysis of the main elements of the data management policy that will be used by the applications with regard to all the datasets that will be generated by the project The DMP is not a fixed document but evolves during the lifespan of the project More developed versions of the plan can therefore be included as additional deliverables at later stages According to the Guidelines on Data Management in Horizon 2020 the DMP should address data set reference and name data set description standards and metadata data sharing and archiving and preservation including storage and backup on a dataset by dataset basis and should reflect the current status of reflection within the consortium about the data that will be produced

Demonstrator Security Evaluation

This deliverable will contain the results of the security evaluation & testing campaign led in T4.4.

Report on Selected TRNG and PUF Principles

Stochastic models and embedded tests.

Risk Assessment Plan

The Risk Assessment Plan will include a Critical Path Analysis (CPA) of the main project activities, identifying risk points, and procedures to deal with them. This deliverable is marked with nature “O” (OTHER) and will be accompanied by a small written report outlining its structure and purposes in order to justify the achievement of this deliverable.

Project Quality Plan

The project quality plan (the project handbook) constitutes a set of project templates, explanations on the project management process, review process, quality checks, meeting organisation, which is communicated to all partners. This deliverable is marked with nature “O” (OTHER) and will be accompanied by a small written report outlining its structure and purposes in order to justify the achievement of this deliverable.

Final Report on Data Management

This report will summarize the efforts of the HECTOR consortium to handling of open research data.

Internal and External IT Communication Infrastructure and Project Website

The external IT communication infrastructure constitutes a guideline for communication of the HECTOR project to external target groups including conferences, marketing measures and communication channels. Furthermore this deliverable constitutes the launch of the internal HECTOR communication infrastructure including the establishment of mailing lists or a subversion server, and the HECTOR website. This deliverable is marked with nature “DEC” and will be accompanied by a small written report outlining its structure and purpose in order to justify the achievement of this deliverable.

Demonstrator Platform

This deliverable will consist of the complete setup of the demonstrator platform as output of T4.2 and T4.3 Only the VHDL code corresponding to the deliverable is CO. The accompanied report and the sample data are public.

Publicaciones

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Autores: Rozic Vladimir, Yang Bohan, Dehaene Wim, Verbaudwhede Ingrid
Publicado en: IEEE Int. Symposium on Hardware-Oriented Security and Trust , 2016
Editor: IEEE
DOI: 10.5281/zenodo.55456

Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches

Autores: Gruss Daniel, Spreitzer Raphael, Mangard Stefan
Publicado en: 24th USENIX Security Symposium 2015 , 2015
Editor: USENIX
DOI: 10.5281/zenodo.55454

Square Attack on 7-Round Kiasu-BC

Autores: Dobraunig Christoph, Eichlseder Maria, Mendel Florian
Publicado en: 14th International Conference on Applied Cryptography and Network Security , 2016
Editor: -
DOI: 10.5281/zenodo.55445

Canary Numbers: Design for Light-weight Online Testability of True Random Number Generators

Autores: Rozic Vladimir, Yang Bohan, Mentens Nele, Verbauwhede Ingrid
Publicado en: Random Bit Generation Workshop 2016 , 2016
Editor: -
DOI: 10.5281/zenodo.56625

Efficient Fuzzy Extraction of PUF-Induced Secrets: Theory and Applications

Autores: Delvaux Jeroen, Gu Dawu, Verbaudwhede Ingrid, Hiller Matthias, Yu Meng-Day
Publicado en: Conference on Cryptographic Hardware and Embedded Systems 2016 , 2016
Editor: Springer
DOI: 10.5281/zenodo.55449

TOTAL: TRNG On-the-fly Testing for Attack detection using Lightweight hardware

Autores: Yang Bohan, Rozic Vladimir, Mentens Nele, Dehaene Wim, Verbaudwhede Ingrid
Publicado en: Design, Automation & Test in Europe Conference & Exhibition , 2016
Editor: IEEE
DOI: 10.5281/zenodo.55455

Flush+Flush: A Fast and Stealthy Cache Attack

Autores: Gruss Daniel, Maurice Clementine, Wagner Klaus, Mangard Stefan
Publicado en: 13th Conference on Detection of Intrusions and Malware & Vulnerability Assessment , 2016
Editor: -
DOI: 10.5281/zenodo.55446

Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript

Autores: Gruss Daniel, Maurice Clementine, Mangard Stefan
Publicado en: 13th Conference on Detection of Intrusions and Malware & Vulnerability Assessment , 2016
Editor: -
DOI: 10.5281/zenodo.55447

A Physical Approach for Stochastic Modeling of TERO-based TRNG

Autores: Haddad, Patrick; Fischer, Viktor; Bernard, Florent; Nicolai, Jean
Publicado en: Cryptographic Hardware and Embedded Systems -- CHES 2015, 2015, Página(s) 357-372, ISBN 978-3-662-48323-7
Editor: Springer Berlin Heidelberg
DOI: 10.5281/zenodo.60900

Practical Memory Deduplication Attacks in Sandboxed Javascript

Autores: Gruss, Daniel; Bidner, David; Mangard, Stefan
Publicado en: Computer Security -- ESORICS 2015, 2015, Página(s) 108-122, ISBN 978-3-319-24173-9
Editor: Springer International Publishing
DOI: 10.5281/zenodo.55453

Forgery and Subkey Recovery on CAESAR candidate iFeed

Autores: Schroé, Willem; Mennink, Bart; Andreeva, Elena; Preneel, Bart
Publicado en: Selected Areas in Cryptography - SAC 2015, 2015, Página(s) 197-204, ISBN 978-3-319-31301-6
Editor: Springer International Publishing
DOI: 10.5281/zenodo.55452

On the Impact of Known-Key Attacks on Hash Functions

Autores: Mennink, Bart; Preneel, Bart
Publicado en: Advances in Cryptology – ASIACRYPT 2015, 2015, Página(s) 59-84, ISBN 978-3-662-48800-3
Editor: Springer Berlin Heidelberg
DOI: 10.5281/zenodo.55450

Higher-Order Threshold Implementation of the AES S-Box

Autores: De Cnudde, Thomas; Bilgin, Begül; Reparaz, Oscar; Nikov, Ventzislav; Nikova, Svetla
Publicado en: Smart Card Research and Advanced Applications, 2015, Página(s) 259-272, ISBN 978-3-319-31271-2
Editor: Springer International Publishing
DOI: 10.5281/zenodo.58086

ARMageddon: Cache Attacks on Mobile Devices

Autores: Lipp, Moritz; Gruss, Daniel; Spreitzer, Raphael; Maurice, Clémentine; Mangard, Stefan
Publicado en: 25th Annual USENIX Security Symposium, 2016
Editor: -
DOI: 10.5281/zenodo.59889

Statistical Fault Attacks on Nonce-Based Authenticated Encryption Schemes

Autores: Dobraunig, Christoph; Eichlseder, Maria; Korak, Thomas; Lomne, Victor; Mendel, Florian
Publicado en: 22nd Annual International Conference on the Theory and Applications of Cryptology and Information Security (Asiacrypt2016), 2016
Editor: -
DOI: 10.5281/zenodo.154485

Analysis of the Kupyna-256 Hash Function

Autores: Dobraunig, Christoph; Eichlseder, Maria; Mendel, Florian
Publicado en: ACM SIGSOFT International Symposium on the Foundations of Software Engineering, 2016
Editor: -
DOI: 10.5281/zenodo.121361

Evaluation of AIS-20/31 compliant TRNG cores implemented on FPGAs

Autores: Petura, Oto; Mureddu, Ugo; Bochard, Nathalie; Fischer, Viktor; Bossuet, Lilian
Publicado en: https://hal.archives-ouvertes.fr/hal-01382990, Edición 1, 2018
Editor: -
DOI: 10.5281/zenodo.1287567

Upper Bounds on The Min-Entropy of RO Sum, Arbiter, Feed-Forward Arbiter, and S-ArbRO PUFs

Autores: Jeroen Delvaux; Dawu Gu; Ingrid Verbauwhede
Publicado en: Edición 3, 2016
Editor: IEEE
DOI: 10.5281/zenodo.375498

A comparison of PUF cores suitable for FPGA devices

Autores: Mureddu, Ugo; Bossuet, Lilian; Fischer, Viktor
Publicado en: Conference on trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE), 2016, Barcelone, Spain. 2016, Edición 4, 2016
Editor: -
DOI: 10.5281/zenodo.1287571

ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling

Autores: Yang, Bohan; Rozic, Vladimir; Grujic, Milos; Mentens, Nele; Verbauwhede, Ingrid
Publicado en: Edición 1, 2018
Editor: Zenodo
DOI: 10.5281/zenodo.1434083

Two Methods of the Clock Jitter Measurement Aimed at Embedded TRNG Testing

Autores: Petura , Oto; Laban , Marek; Noumon Allini , Elie ,; Fischer , Viktor
Publicado en: Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2018), Edición 1, 2018
Editor: Zenodo
DOI: 10.5281/zenodo.1284209

ISAP -- Towards Side-Channel Secure Authenticated Encryption

Autores: Christoph Dobraunig; Maria Eichlseder; Stefan Mangard; Florian Mendel; Thomas Unterluggauer
Publicado en: 2519-173X, Edición 3, 2017
Editor: -
DOI: 10.13154/tosc.v2017.i1.80-105

Masking AES With d+1 Shares in Hardware

Autores: Thomas De Cnudde, Oscar Reparaz, Begül Bilgin, Svetla Nikova, Ventzislav Nikov, Vincent Rijmen
Publicado en: Proceedings of the 2016 ACM Workshop on Theory of Implementation Security - TIS'16, 2016, Página(s) 43-43, ISBN 9781-450345750
Editor: ACM Press
DOI: 10.1145/2996366.2996428

Design and Testing Methodologies for True Random Number Generators Towards Industry Certification

Autores: Balasch, Josep; Bernard, Florent; Fischer, Viktor; Grujic, Milos; Laban, Marek; Petura, Oto; Rozic, Vladimir; Van Battum, Gerard; Verbauwhede, Ingrid; Wakker, Marnix; Yang, Bohan
Publicado en: Edición 2, 2018
Editor: Zenodo
DOI: 10.5281/zenodo.1289440

A Methodology for the Characterization of Leakages in Combinatorial Logic

Autores: Guido Bertoni; Marco Martinoli
Publicado en: Edición 3, 2016
Editor: Springer
DOI: 10.5281/zenodo.571605

Optimization of the PLL configuration in a PLL-based TRNG design

Autores: Elie Noumon Allini, Oto Petura, Viktor Fischer, Florent Bernard
Publicado en: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Página(s) 1265-1270, ISBN 978-3-9819263-0-9
Editor: IEEE
DOI: 10.23919/DATE.2018.8342209

Exploring active manipulation attacks on the TERO random number generator

Autores: Cao, Yang; Rozic, Vladimir; Yang, Bohan; Balasch, Josep; Verbauwhede, Ingrid
Publicado en: Edición 4, 2016
Editor: IEEE
DOI: 10.5281/zenodo.154591

Modular evaluation platform for evaluation and testing of physically unclonable functions

Autores: Marek Laban, Milos Drutarovsky, Viktor Fischer, Michal Varchola
Publicado en: 2018 28th International Conference Radioelektronika (RADIOELEKTRONIKA), 2018, Página(s) 1-6, ISBN 978-1-5386-2485-2
Editor: IEEE
DOI: 10.1109/RADIOELEK.2018.8376359

A Closer Look at the Delay-Chain based TRNG

Autores: Milos Grujic, Vladimir Rozic, Bohan Yang, Ingrid Verbauwhede
Publicado en: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Página(s) 1-5, ISBN 978-1-5386-4881-0
Editor: IEEE
DOI: 10.1109/ISCAS.2018.8351222

A comprehensive hardware/software infrastructure for IP cores design protection

Autores: Brice Colombier, Lilian Bossuet, Ugo Mureddu, David Hely
Publicado en: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, Página(s) 263-266, ISBN 978-1-5386-2656-6
Editor: IEEE
DOI: 10.1109/FPT.2017.8280156

An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order

Autores: Hannes Gross; Stefan Mangard; Thomas Korak
Publicado en: Edición 3, 2017
Editor: Springer LNCS
DOI: 10.5281/zenodo.574261

Towards inter-vendor compatibility of true random number generators for FPGAs

Autores: Milos Grujic, Bohan Yang, Vladimir Rozic, Ingrid Verbauwhede
Publicado en: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Página(s) 1520-1523, ISBN 978-3-9819263-0-9
Editor: IEEE
DOI: 10.23919/DATE.2018.8342256

Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs

Autores: Ugo Mureddu, Oto Petura, Nathalie Bochard, Lilian Bossuet, Viktor Fischer
Publicado en: 2017 IEEE 2nd International Verification and Security Workshop (IVSW), 2017, Página(s) 146-151, ISBN 978-1-5386-1708-3
Editor: IEEE
DOI: 10.1109/IVSW.2017.8031560

A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

Autores: Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, Lilian Bossuet
Publicado en: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016, Página(s) 1-10, ISBN 978-2-8399-1844-2
Editor: IEEE
DOI: 10.1109/FPL.2016.7577379

Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR

Autores: Daniel Gruss; Clémentine Maurice; Moritz Lipp; Stefan Mangard; Anders Fogh
Publicado en: Edición 4, 2016
Editor: ACM
DOI: 10.5281/zenodo.375513

Practical Key-Recovery Attack on MANTIS-5

Autores: Christoph Dobraunig; Maria Eichlseder; Daniel Kales; Florian Mendel
Publicado en: 2519-173X, Edición 3, 2017
Editor: -
DOI: 10.5281/zenodo.574265

Physically Unclonable Function Using CMOS Breakdown Position

Autores: Kai-Hsin Chuang; Erik Bury; Robin Degraeve; Ben Kaczer; Guido Groeseneken; Ingrid Verbauwhede; Dimitri Linten
Publicado en: Edición 2, 2017
Editor: IEEE
DOI: 10.5281/zenodo.571735

Drammer: Deterministic Rowhammer Attacks on Mobile Platforms

Autores: Daniel Gruss; Clémentine Maurice; Victor van der Veen; Herbert Bos; Kaveh Razavi; Cristiano Giuffrida; Yanick Fratantonio; Martina Lindorfer; Giovanni Vigna
Publicado en: Edición 4, 2016
Editor: ACM
DOI: 10.5281/zenodo.375506

Platform for Testing and Evaluation of PUF and TRNG Implementations in FPGAs

Autores: Marek Laban; Milos Drutarovsky; Viktor Fischer; Michal Varchola
Publicado en: Edición 4, 2016
Editor: -
DOI: 10.5281/zenodo.163283

Reconciling d+1 Masking in Hardware and Software

Autores: Hannes Gross; Stefan Mangard
Publicado en: Edición 2, 2017
Editor: Springer LNCS
DOI: 10.5281/zenodo.897934

Another Flip in the Wall of Rowhammer Defenses

Autores: Daniel Gruss, Moritz Lipp, Michael Schwarz, Daniel Genkin, Jonas Juffinger, Sioli O'Connell, Wolfgang Schoechl, Yuval Yarom
Publicado en: 2018 IEEE Symposium on Security and Privacy (SP), 2018, Página(s) 245-261, ISBN 978-1-5386-4353-2
Editor: IEEE
DOI: 10.1109/SP.2018.00031

Fast Leakage Assessment

Autores: Oscar Reparaz; Benedikt Gierlichs; Ingrid Verbauwhede
Publicado en: Edición 2, 2017
Editor: Zenodo
DOI: 10.5281/zenodo.897902

The impact of pulsed Electromagnetic Fault Injection on true random number generators

Autores: Madau, Maxime; Agoyan, Michel; Balasch, Josep; Grujic, Milos; Haddad, Patrick; Maurine, Philippe; Rozic, Vladimir; Singelee, Dave; Yang, Bohan; Verbauwhede, Ingrid
Publicado en: Edición 1, 2018
Editor: Zenodo
DOI: 10.5281/zenodo.1434074

Complete activation scheme for FPGA-oriented IP cores design protection

Autores: Colombier , Brice; Mureddu , Ugo; Laban , Marek; Petura , Oto; Bossuet , Lilian; Fischer , Viktor
Publicado en: https://hal-ujm.archives-ouvertes.fr/ujm-01588947, Edición 2, 2017
Editor: Zenodo
DOI: 10.5281/zenodo.574260

Optimization of the PLL based TRNG design using the genetic algorithm

Autores: Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer
Publicado en: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, Página(s) 1-4, ISBN 978-1-4673-6853-7
Editor: IEEE
DOI: 10.1109/ISCAS.2017.8050839

Complete activation scheme for IP design protection

Autores: Colombier, Brice; Mureddu, Ugo; Laban, Marek; Petura, Oto; Bossuet, Lilian; Fischer, Viktor
Publicado en: https://hal-ujm.archives-ouvertes.fr/ujm-01575569, Edición 2, 2017
Editor: -
DOI: 10.5281/zenodo.574260

Statistical Fault Attacks on Nonce-Based Authenticated Encryption Schemes

Autores: Dobraunig, Christoph; Eichlseder, Maria; Korak, Thomas; Lomne, Victor; Mendel, Florian
Publicado en: Edición 4, 2016
Editor: Springer
DOI: 10.5281/zenodo.154487

KeyDrown: Eliminating Software-Based Keystroke Timing Side-Channel Attacks

Autores: Michael Schwarz, Moritz Lipp, Daniel Gruss, Samuel Weiser, Clementine Maurice, Raphael Spreitzer, Stefan Mangard
Publicado en: Proceedings 2018 Network and Distributed System Security Symposium, 2018, ISBN 1-891562-49-5
Editor: Internet Society
DOI: 10.14722/ndss.2018.23027

Evaluation and monitoring of free running oscillators serving as source of randomness

Autores: Allini, Elie Noumon; Skórski, Maciej; Petura, Oto; Bernard, Florent; Laban, Marek; Fischer, Viktor
Publicado en: Edición 1, 2018
Editor: Zenodo
DOI: 10.5281/zenodo.1443138

The Monte Carlo PUF

Autores: Vladimir Rozic; Bohan Yang; Jo Vliegen; Nele Mentens; Ingrid Verbauwhede
Publicado en: Edición 2, 2017
Editor: Zenodo
DOI: 10.5281/zenodo.897887

On-chip jitter measurement for true random number generators

Autores: Bohan Yang; Vladimir Rozic; Milos Grujic; Nele Mentens; Ingrid Verbauwhede
Publicado en: Edición 2, 2017
Editor: Zenodo
DOI: 10.5281/zenodo.897896

Cryptanalysis of Simpira v1

Autores: Christoph Dobraunig; Maria Eichlseder; Florian Mendel
Publicado en: Edición 1, 2017
Editor: Springer LNCS
DOI: 10.5281/zenodo.375528

Evariste III: A new multi-FPGA system for fair benchmarking of hardware dependent cryptographic primitives

Autores: Bochard, Nathalie; Marchand, Cedric; Petura, Oto; Bossuet, Lilian; Fischer, Viktor
Publicado en: Workshop on Cryptographic Hardware and Embedded Systems, 2015
Editor: -
DOI: 10.5281/zenodo.61294

Sources of Randomness in Digital Devices and their Testability

Autores: Fischer, Viktor
Publicado en: Random Bit Generation Workshop 2016, 2016
Editor: -
DOI: 10.5281/zenodo.58127

D6.2 - Project Quality Plan

Autores: Corinna Kudler; Kathrin Assmayr; Martin Deutschmann; Nele Mentens
Publicado en: Edición 62, 2015
Editor: Zenodo
DOI: 10.5281/zenodo.801213

D2.1 - Report on Selected TRNG and PUF Principles

Autores: Martin DEUTSCHMANN; Sandra LATTACHER; Jeroen DELVAUX; Vladimir ROZIC; Bohan YANG; Dave SINGELEE; Lilian BOSSUET; Viktor FISCHER; Ugo MUREDDU; Oto PETURA; Alexandre ANZALA YAMAJAKO; Bernard KASSER; Gerard BATTUM
Publicado en: Edición 10, 2016
Editor: -
DOI: 10.5281/zenodo.801083

D5.1 - Internal and External IT Communication Infrastructure and Project Website

Autores: Corinna KUDLER; Martin DEUTSCHMANN; Mario MÜNZER; Felix STORNIG; Thomas KORAK
Publicado en: Edición 16, 2015
Editor: -
DOI: 10.5281/zenodo.801166

D6.1 - Risk Assessment Plan

Autores: Sandra Lattacher; Martin Deutschmann; Marion Buchacher; Sandra Moschitz; Jan Seda; Dave Singelee; Viktor Fischer; Bernard Kasser
Publicado en: Edición 2, 2016
Editor: Zenodo
DOI: 10.5281/zenodo.801200

D5.2 - Data Management Plan (DMP)

Autores: Martin Deutschmann; Corinna Kudler; Sandra Lattacher; Dave Singelee; Ingrid Verbauwhede; Viktor Fischer; Alexandre Anzala Yamayako; Bernard Kasser; Guido Bertoni; Michal Varchola; Gerard Battum
Publicado en: Edición 2, 2015
Editor: Zenodo
DOI: 10.5281/zenodo.801182

Clustering Related-Tweak Characteristics: Application to MANTIS-6

Autores: Maria Eichlseder, Daniel Kales
Publicado en: IACR Transactions on Symmetric Cryptology, 2018, ISSN 2519-173X
Editor: Ruhr-Universität Bochum
DOI: 10.13154/tosc.v2018.i2.111-132

Differential Cryptanalysis of Symmetric Primitives

Autores: Eichlseder, Maria
Publicado en: Edición 1, 2018
Editor: Zenodo
DOI: 10.5281/zenodo.1288325

Security Analysis of PUF-Based Key Generation and Entity Authentication

Autores: Jeroen Delvaux
Publicado en: Edición 2, 2017
Editor: -
DOI: 10.5281/zenodo.897914

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

Autores: Cedric Marchand, Lilian Bossuet, Ugo Mureddu, Nathalie Bochard, Abdelkarim Cherkaoui, Viktor Fischer
Publicado en: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Edición 37/1, 2018, Página(s) 97-109, ISSN 0278-0070
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2017.2702607

Symbolic Analysis of Higher-Order Side Channel Countermeasures

Autores: Elia Bisi, Filippo Melzani, Vittorio Zaccaria
Publicado en: IEEE Transactions on Computers, Edición 66/6, 2017, Página(s) 1099-1105, ISSN 0018-9340
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TC.2016.2635650

From Physical to Stochastic Modeling of a TERO-Based TRNG

Autores: Florent Bernard, Patrick Haddad, Viktor Fischer, Jean Nicolai
Publicado en: Journal of Cryptology, 2018, ISSN 0933-2790
Editor: Springer Verlag
DOI: 10.1007/s00145-018-9291-2

Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices

Autores: Raphael Spreitzer, Veelasha Moonsamy, Thomas Korak, Stefan Mangard
Publicado en: IEEE Communications Surveys & Tutorials, Edición 20/1, 2018, Página(s) 465-488, ISSN 1553-877X
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/COMST.2017.2779824

Lightweight Prediction-Based Tests for On-Line Min-Entropy Estimation

Autores: Milos Grujic, Vladimir Rozic, Bohan Yang, Ingrid Verbauwhede
Publicado en: IEEE Embedded Systems Letters, Edición 9/2, 2017, Página(s) 45-48, ISSN 1943-0663
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/LES.2017.2687082

Key Reconciliation Protocols for Error Correction of Silicon PUF Responses

Autores: Brice Colombier, Lilian Bossuet, Viktor Fischer, David Hely
Publicado en: IEEE Transactions on Information Forensics and Security, Edición 12/8, 2017, Página(s) 1988-2002, ISSN 1556-6013
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TIFS.2017.2689726

A unified masking approach

Autores: Hannes Gross, Stefan Mangard
Publicado en: Journal of Cryptographic Engineering, Edición 8/2, 2018, Página(s) 109-124, ISSN 2190-8508
Editor: Springer Science + Business Media
DOI: 10.1007/s13389-018-0184-y

Spectral features of higher-order side-channel countermeasures

Autores: Zaccaria, Vittorio; Melzani, Filippo; Bertoni, Guido
Publicado en: IEEE Transactions on Computers, Edición 1, 2018, ISSN 0018-9340
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.5281/zenodo.1134753

Rotational Cryptanalysis in the Presence of Constants

Autores: Ashur, Tomer; Liu, Yunwen
Publicado en: IACR Transactions on Symmetric Cryptology, Edición 1, 2016, ISSN 2519-173X
Editor: Ruhr-Universität Bochum
DOI: 10.13154/tosc.v2016.i1.57-70

Breaching the Privacy of Israel’s Paper Ballot Voting System

Autores: Tomer Ashur, Orr Dunkelman, Nimrod Talmon
Publicado en: Electronic Voting, Edición 10141, 2017, Página(s) 108-124, ISBN 978-3-319-52239-5
Editor: Springer International Publishing
DOI: 10.1007/978-3-319-52240-1_7

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