Periodic Reporting for period 1 - Wave-Locked Loop (Wave-Locked Loop for Frequency Synthesis (WLL))
Período documentado: 2017-04-01 hasta 2019-03-31
2. To support the upcoming 5G standard, mm-wave Class-F LC-based DCO with low flicker noise corner will be studied has been studied and verified with chip measurement. Class-F oscillator shows competitive performance compared with other oscillator classes but it is much more robust to power supply noise. Since flicker noise corner is usually high in mm-wave oscillators which could be the main noise contributor, we have investigated flicker-noise corner reduction at mm-wave in which the consideration of common-mode inductance and capacitance in the transformer and switched capacitor are carefully modelled and simulated to achieve high common-mode impedance at second harmonic. This results in a flicker noise corner of 130kHz while maintain phase noise figure-of-merit on-par with the state-of-the-art.
3. The study of low-supply ADPLL has been investigated. While digitally-controlled oscillator (DCO) and digital power amplifier (DPA) can directly operate at low supply, time-to-digital converter (TDC) and all digital blocks need higher supply voltage to operate. In particular, if TDC is operated at relatively low supply, its resolution degrades and results in a degradation of in-band phase noise of an ADPLL. Moreover, traditional approach requires additional digital gain calibration to maintain ADPLL performance across process-temperature-voltage (PVT) variations.
4. For energy-efficient 30GHz harmonic extractor, we proposed injection-locked third-harmonic extractor technique which reduce power consumption when compared with traditional approach while maintain output power level at acceptable performance.
5. The study of the oversampled oscillator waveform for precise phase/frequency and amplitude detections and system integration will be studied over a variation of several nonlinearities factor (WP1), i.e. harmonically distorted (both intentional and unintentional) input waveform, nonlinear delays in oversampling clocks, and resolution of ADC. Our study shows finer than 1 ps resolution even with 10% delay error in sampling clocks, and distortion from input waveform. Thus, this approach is suitable for phase detection in all-digital phase-looked loop and it is much more roust and offer much larger dynamic range compared with traditional sub-sampling phase detector.