'Declarative aspects of multicore programming', Austin, US
Many chip manufactures are turning to multicore processor designs as a way to get performance in their desktop, enterprise, and mobile processors. This new trend may not succeed in the long-term if mainstream applications cannot be parallelised to take advantage of tens and eventually hundreds of hardware threads.
Multicore architectures differ in significant ways from their shared memory predecessors. For example, the communication to compute bandwidth ratio is likely to be higher, which will positively impact performance. More generally, multicore architectures introduce several new dimensions of variability in both performance guarantees and architectural contracts, such as the memory model, that may not stabilise for several product lifecycles.
This will be the sixth in a series of workshops seeking to explore ideas in declarative programming language design that will greatly simplify programming for multicore architectures, and more generally for tightly-coupled, parallel architectures.For further information, please visit: http://damp2011.cs.uchicago.edu/(opens in new window)