Skip to main content

Controlling leakage power in NanoCMOS SoCs

Objective

With the advent of nanometric devices, the relevance of leakage power has grown tremendously. All technology roadmaps, as well as the results from advanced semiconductor labs indicate leakage as the real showstopper for the future generations of nanoelectronic circuits if proper counter-measures will not be taken. To be successful, and thus leading to the capability of fabricating chips with sub-65nm technologies, such counter-measures must be rooted in the design domain, as process improvement will not be sufficient to cope with the increased leakage currents in MOSFETs. In other terms, time has come for considering leakage reduction also a design problem, and not only a technology problem.

CLEAN will contribute in a decisive way to the solution of the problem of controlling leakage currents in CMOS designs below 65nm, which is of strategic importance in the ASIC and SoC design landscape. The RandD effort will crystallize around the development of new leakage models for nanometric technologies usable at different levels of abstraction, from device to behavioral, innovative circuit and architectural solutions for efficient leakage management, novel methods and prototype EDA tools for automatic leakage minimization. Such methods and tools will be integrated into commercial EDA frameworks, thus providing comprehensive solutions for power-driven design.

The CLEAN Consortium features the right mix of competence (semiconductor vendors, EDA vendors, research institutes) and the appropriate mobilization of resources to guarantee the successful achievement of all the project objectives. Tight links to on-going European projects targeting advanced silicon technology development (e.g. the NanoCMOS IP and its possible successor, PullNano) will guarantee synergy and convergence of objectives, towards the establishment of design capabilities that will be key for consolidating and growing the European competitiveness in the nanoelectronics business of the future.

Funding Scheme

IP - Integrated Project

Coordinator

STMICROELECTRONICS SRL
Address
Via Olivetti 2
20041 Agrate Brianza
Italy

Participants (13)

BUDAPESTI MUSZAKI ES GAZDASAGTUDOMANYI EGYETEM
Hungary
Address
Muegyetem Rakpart 3
1111 Budapest
BULLDAST S.R.L.
Italy
Address
Via Sforzesca 3
10100 Torino
CHIPVISION DESIGN SYSTEMS AG
Germany
Address
Fritz Bock Strasse 5
26121 Oldenburg
COMMISSARIAT A L'ENERGIE ATOMIQUE
France
Address
Batiment Le Ponant D, 25 Rue Leblanc
75015 Paris Cedex 15
CONSORZIO PER LA RICERCA E L'EDUCAZIONE PERMANENTE, TORINO
Italy
Address
Corso Duca Degli Abruzzi 24
10129 Torino
DANMARKS TEKNISKE UNIVERSITET
Denmark
Address
Anker Engelundsvej 1, Bygning 101A
2800 Kgs. Lyngby
EDACENTRUM GMBH
Germany
Address
Schneiderberg 32
30167 Hannover
INFINEON TECHNOLOGIES AG
Germany
Address

81726 Muenchen
OFFIS EV
Germany
Address
Escherweg 2
000 Oldenburg
POLITECHNIKA WARSZAWSKA
Poland
Address
Plac Politechniki 1
Warszawa
POLITECNICO DI TORINO
STMICROELECTRONICS SA
France
Address
29 Boulevard Romain Rolland
92120 Montrouge
UNIVERSITAT POLITECNICA DE CATALUNYA