European citizens are now living in a world of "pervasive computing", where virtually every object has a processing power. Undoubtedly, computing devices are more ubiquitous and interconnected than ever, fulfilling the most varied tasks with little human help.
The size of these "pervasive computing" networks is significantly increasing, as well as the variety of the computing devices, both at chip (multicore and reconfigurable architectures) and system level (distributed processing). As their scope of application broadens, processing resources require greater flexibility and scalability to meet the various needs of users.
By the year 2020, embedded computing architectures as envisaged today will be far more complex, due mainly to the convergence of High Performance Computing and Embedded Computing technologies, the emergence of new hardware technologies and finally, the multiplication of heterogeneous computing devices.
The purpose of the AETHER project is to show that self-adaptive computing architectures can be a powerful approach to simultaneously addressing the major problems raised by pervasive computing. AETHER's main objectives are to study, evaluate and propose novel computing architectures responding to the most demanding embedded applications in the next 10+ years.
In particular, the AETHER project aims to tackle the issues related to the performance and technological scalability, increased complexity and programmability of future embedded computing architectures by introducing self-adaptive technologies in computing resources. The AETHER consortium will study and propose self-adaptive networked entities based on reconfigurable computing architectures, and study their impact at various levels of the computing chain such as operating environments, programming tools and application design. The potential benefits of the proposed approach will be assessed and validated with industrial partners on realistic application scenarios.
Fields of science
- natural sciencescomputer and information sciencessoftware
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsignal processing
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringdigital electronics
Funding SchemeIP - Integrated Project
Paris Cedex 16
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Nice - Cedex 2
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