The competitive advantage of European industry in embedded system design is constantly challenged by emerging as well as other industrialized economies. The leading edge must be strengthened by boosting productivity, mastering growing complexity, and maintaining high quality of embedded systems.
The project INTEREST aims to overcome the current lack of integration and interoperability of tools for developing Embedded Systems software. The partners in the proposed project comprise a unique group of European tool vendors that jointly address the Embedded Systems design flow.
The following capabilities will be targeted:
- Mapping of a logical architecture, i.e. the structure of the control algorithms, to a technical architecture.
- Analysis of Timing related objectives for System and Nodes
- Tool integration along the "V" development cycle, spanning all the analysis, system design, module design, implementation (including certified code generation), functional testing, module testing, system testing and requirements testing
It will achieve its aims by creating techniques for improved interoperability (the INTEREST development framework) between European embedded systems design, code generation and verification COTS tools, which could not previously been achieved:
- SCADE from ESTEREL TECHNOLOGIES
- ASCET and INTECRIO from ETAS
- DESIGNER Pro from DECOMSYS
- Dependable COTS code (such as UNIS hardware abstraction layer COTS)
The project will develop novel techniques for system-level and node-level analysis of non-functional properties, such as Worst Case Execution Timing, Stack and schedulability.
These Analysis tools from ABSINT, EVIDENCE and SYMTAVISION will be then integrated into the INTEREST development framework. INTEREST will thus contribute securing Europe's competitiveness and independence in the Embedded Systems field.
Funding SchemeSTREP - Specific Targeted Research Project
624 00 Brno