Periodic Reporting for period 1 - L2D2 (Laser digital transfer of 2D materials enabled photonics: from the lab 2 the fab)
Reporting period: 2022-10-01 to 2023-09-30
The graphene and 2D materials market comprise an emerging niche within the semiconductor industry and 2D materials interfaced with silicon will enable to overcome major limitations in optoelectronics and photonics. The current wafer scale manufacturing method for electronic/photonic grade graphene is based on chemical vapour deposition (CVD), which can provide up to 200 mm graphene wafers. After the graphene growth within the CVD reactor, graphene has to be transferred onto relevant substrates for the application such as Si photonic dies or CMOS wafers. There is a significant number of steps involved in this transfer process: single layer graphene (SLG) is grown on copper substrates and then a sacrificial polymer layer is applied before proceeding to etching/detaching the copper. Once the etching is completed the polymer/graphene is placed on the final application substrate. Finally, the polymer layer has to be eliminated (via dissolution in organic solvents) in order to obtain graphene on the application substrate. Therefore, a green and solvent-free technology offering the solution to transfer single layer graphene and 2D materials in a single step, preserving the same quality in wafer scale processing is a major breakthrough.
In this respect, L2D2 will deliver a two-fold technological breakthrough:
1. The technology to upscale Gr and other 2D materials on the 8-inch scale at industrial grade quality
2. A laser-based, single-step and green printing solution for wafer-scale integration of 2D materials
The printing will be implemented via the Laser Digital Transfer (LDT) technique for the successful digital transfer of graphene, and a wide range of other 2D materials including hBN, MoTe2 and WS2. The consortium has successfully demonstrated at TRL4 that using LDT, the CVD grown graphene and 2D materials on 3-inch wafers size can be transferred on SiO2/Si and flexible polymer substrates, or samples with patterned structures with lateral resolution down to 10 μm. The added value of the LDT integration of heterostructures 2D materials on Si, enabling direct emission has also been demonstrated within LEAF-2D, and laid the foundation for the wafer scale development of on-chip Si emitters.
In this respect, L2D2 will deliver a two-fold technological breakthrough:
1. The technology to upscale Gr and other 2D materials on the 8-inch scale at industrial grade quality
2. A laser-based, single-step and green printing solution for wafer-scale integration of 2D materials
The printing will be implemented via the Laser Digital Transfer (LDT) technique for the successful digital transfer of graphene, and a wide range of other 2D materials including hBN, MoTe2 and WS2. The consortium has successfully demonstrated at TRL4 that using LDT, the CVD grown graphene and 2D materials on 3-inch wafers size can be transferred on SiO2/Si and flexible polymer substrates, or samples with patterned structures with lateral resolution down to 10 μm. The added value of the LDT integration of heterostructures 2D materials on Si, enabling direct emission has also been demonstrated within LEAF-2D, and laid the foundation for the wafer scale development of on-chip Si emitters.
WP1. The technical management activities have been meticulous and all deliverable due for the reporting period have been submitted, and at least 1 teleconference per month involving the General Assembly of the consortium has taken place. Regarding the IP management, significant progress has been made by the consortium in terms of clarifying the current IP status, drafting a realistic strategy for reinforcing the existing IP and towards screening the newly produced results for future IP.
WP2, related to the materials and process specifications, has been completed based on the DoA. Indeed, the specifications for synthesis and upscaling 2D materials have been set, together with the quality standards and tolerances and the LDT process and system requirements have been specified. Of course, the specifications and the requirements addressed within WP2 will be continuously monitored and updated whenever new outcomes of the project dictate novel or more specific approaches.
WP3. Suitable Cu donor substrates for LIFT and LIBT (Cu thickness and roughness) have been developed, on top of which, high quality graphene has been grown. Isolated WS2 crystals growth on sapphire has been achieved by CVD and their transfer to Ni (50nm)/quartz for LIFT. Graphene and 2D materials quality evaluation (Raman, PL, optical microscopy and device fabrication) has been thoroughly implemented.
WP4. LDT technology demonstrations of different pixel sizes of Graphene, Graphene and hBN heterostructures, the application of Graphene as FET channels and the successful demonstration of LDT of WS2 pixels. Additionally, a yield analysis of the LDT process on Si substrates has been carried out, relying on the analysis of 1000 pixels printed across a 1-inch receiver substrate.
WP5. MLNX evaluated the available silicon photonics manufacturing options, using knowledge that was obtained during the work in LEAF2D. The finalized design was checked for DRC violations and submitted to the foundry for further examination. It was then accepted for fabrication. The chips were fabricated and delivered to MLNX labs in less than 2.5 months and were, thereafter, sent to NTUA and BIU for experiments.
WP6. During the first reporting period the consortium established a clear dissemination and communication plan, regularly updated project stakeholders and ensured optimal internal communication by organizing monthly teleconferences and other means of effective interactios and by developing and sharing projects templates. The visual identity has been fully created based on a functional website including a restricted area and active social media accounts. The project partners were assisted to effectively identify and exploit project results.
WP7. The first drafts of a business model and a business plan have been developed during the first reporting period (D7.3 and D7.2). The consortium partners have discussed extensively during the monthly teleconferences about the optimal exploitation paths for the L2D2 outcomes. A concrete Transition Plan has been been drafted following detailed internal innovation surveys aiming to identify all the L2D2-borne exploitable innovations and how they should be best exploited. A targeted market analysis will be performed during the third year of the project, however the consortium has already started to explore the market through targeted contacts with key industrial partners.
WP2, related to the materials and process specifications, has been completed based on the DoA. Indeed, the specifications for synthesis and upscaling 2D materials have been set, together with the quality standards and tolerances and the LDT process and system requirements have been specified. Of course, the specifications and the requirements addressed within WP2 will be continuously monitored and updated whenever new outcomes of the project dictate novel or more specific approaches.
WP3. Suitable Cu donor substrates for LIFT and LIBT (Cu thickness and roughness) have been developed, on top of which, high quality graphene has been grown. Isolated WS2 crystals growth on sapphire has been achieved by CVD and their transfer to Ni (50nm)/quartz for LIFT. Graphene and 2D materials quality evaluation (Raman, PL, optical microscopy and device fabrication) has been thoroughly implemented.
WP4. LDT technology demonstrations of different pixel sizes of Graphene, Graphene and hBN heterostructures, the application of Graphene as FET channels and the successful demonstration of LDT of WS2 pixels. Additionally, a yield analysis of the LDT process on Si substrates has been carried out, relying on the analysis of 1000 pixels printed across a 1-inch receiver substrate.
WP5. MLNX evaluated the available silicon photonics manufacturing options, using knowledge that was obtained during the work in LEAF2D. The finalized design was checked for DRC violations and submitted to the foundry for further examination. It was then accepted for fabrication. The chips were fabricated and delivered to MLNX labs in less than 2.5 months and were, thereafter, sent to NTUA and BIU for experiments.
WP6. During the first reporting period the consortium established a clear dissemination and communication plan, regularly updated project stakeholders and ensured optimal internal communication by organizing monthly teleconferences and other means of effective interactios and by developing and sharing projects templates. The visual identity has been fully created based on a functional website including a restricted area and active social media accounts. The project partners were assisted to effectively identify and exploit project results.
WP7. The first drafts of a business model and a business plan have been developed during the first reporting period (D7.3 and D7.2). The consortium partners have discussed extensively during the monthly teleconferences about the optimal exploitation paths for the L2D2 outcomes. A concrete Transition Plan has been been drafted following detailed internal innovation surveys aiming to identify all the L2D2-borne exploitable innovations and how they should be best exploited. A targeted market analysis will be performed during the third year of the project, however the consortium has already started to explore the market through targeted contacts with key industrial partners.
The exptected results beyond the state of the art will be generated as an outcome of the target innovations of the project:
1. Digital, solvent-free and high-resolution transfer of Gr and other 2D materials (hBN, MoTe2 and WS2) using LDT and donor samples scalable from 2 to 8 inches and compatible with the industrial standards.
2. Defect-free and uniform CVD growth of SLG on evaporated Cu films on quartz or sapphire wafers scalable from 2 to 8 - inches.
3. Ultra-flat and smooth CVD growth of hBN, MoTe2 and WS2 on SOI substrates.
4. Wafer scale integration of hBN, MoTe2 and WS2 enabling chiplets populated with on-chip Si emitters.
1. Digital, solvent-free and high-resolution transfer of Gr and other 2D materials (hBN, MoTe2 and WS2) using LDT and donor samples scalable from 2 to 8 inches and compatible with the industrial standards.
2. Defect-free and uniform CVD growth of SLG on evaporated Cu films on quartz or sapphire wafers scalable from 2 to 8 - inches.
3. Ultra-flat and smooth CVD growth of hBN, MoTe2 and WS2 on SOI substrates.
4. Wafer scale integration of hBN, MoTe2 and WS2 enabling chiplets populated with on-chip Si emitters.