Periodic Reporting for period 1 - COREnext (European Core Technologies for Next Generation Communication-Computing Hardware)
Reporting period: 2023-01-01 to 2024-06-30
The successful and widespread adoption of Beyond 5G and 6G telecommunication systems is not automatic; it requires the development of novel computing and digital infrastructure technologies that can help support a secure and efficient transition. The EU-funded COREnext project will facilitate this goal by developing the necessary digital parts and computing architecture to allow for efficient and safe Beyond 5G and 6G processing. The project will use virtualisation and radio access network technology, and develop innovative components for improved computing and energy efficiency. From antenna to processing, COREnext will apply trust anchors to satisfy security needs in both analog and digital components. Moreover, it will engage telecommunications and microelectronics providers for improved transparency and efficiency.
The COREnext project aims to build a computing architecture and digital components for sustainable and trustworthy B5G and 6G processing. This architecture must support an open, multi-vendor and multi-tenant disaggregated RAN by employing virtualization technology. A step forward in digital component design must be made to address the compute throughput and energy-efficiency requirements. This is addressed by the development of powerful and efficient heterogeneous accelerators, purpose-built for RAN computation and signal processing, as well as ultra-high-speed and low-power interconnects to support disaggregation of compute resources. A cornerstone of the project is trustworthiness. The pervasiveness of B5G and 6G use cases requires deeply embedded hardware trust anchors to fulfil the vision of secure disaggregated compute systems. To realize these goals, the project brings together major telecommunications and microelectronics players as well as academic research partners. A strategic roadmap will offer a transparent path towards future exploitation of the generated research results, fostering a continuing European strategy for the emergence of European digital capabilities in this communication-computing domain.
The COREnext project aims to build a computing architecture and digital components for sustainable and trustworthy B5G and 6G processing. This architecture must support an open, multi-vendor and multi-tenant disaggregated RAN by employing virtualization technology. A step forward in digital component design must be made to address the compute throughput and energy-efficiency requirements. This is addressed by the development of powerful and efficient heterogeneous accelerators, purpose-built for RAN computation and signal processing, as well as ultra-high-speed and low-power interconnects to support disaggregation of compute resources. A cornerstone of the project is trustworthiness. The pervasiveness of B5G and 6G use cases requires deeply embedded hardware trust anchors to fulfil the vision of secure disaggregated compute systems. To realize these goals, the project brings together major telecommunications and microelectronics players as well as academic research partners. A strategic roadmap will offer a transparent path towards future exploitation of the generated research results, fostering a continuing European strategy for the emergence of European digital capabilities in this communication-computing domain.
For Beyond-5G and 6G technology, we expect a growing demand in use cases around personal robotics and similar control applications deployed at a large scale. While these are interesting new applications, they also pose risks for the European economy and society due to their equally large scale impact on personal privacy and safety. In response to this challenge, COREnext brings together 24 European partners, including major representatives from the telecommunications and semiconductor industry, to infuse trustworthiness and sustainability into the technology for future communication networks. Concretely, we intend to address two key technical gaps:
* COREnext will offer efficient and scalable accelerators based on RISC-V extensions and FPGAs as well as power-efficient interconnects to meet sustainability targets while also serving the increasing throughput and latency needs of applications.
* COREnext will develop a trustworthy-by-design architecture, which protects user privacy and platform integrity, while supporting 6G compute demands in edge servers, base stations, and client-side devices.
The work performed in the first 18 months followed a flow from use cases via requirements and a system architecture down to needed component advancements. This technical work is followed by a cadence of deliverables summarizing and contextualizing the achieved results. Main Achievements along this flow of work are:
* Use cases and scenarios were selected which would be used to guide the technical development. Requirements were formulated that will direct the validation of our achievements.
* From these requirements, an architecture for the project was defined, encompassing terminal devices, base stations, and edge cloud. Trustworthiness is considered from the start as a North Star for the technical design. From this architecture, necessary advancements beyond the state of the art are defined for individual key components.
* In particular, we identified four clusters of interacting components requiring innovation beyond the state of the art: efficient signal processing and acceleration, efficient interconnects, infrastructure authentication and attestation, and trusted digital computation.
These key components are now being developed and tested with initial results available. The second half of the project will then see a bottom-up iteration, where component results are used to refine the architecture and requirements are used to validate the delivered advancements beyond the state of the art.
* COREnext will offer efficient and scalable accelerators based on RISC-V extensions and FPGAs as well as power-efficient interconnects to meet sustainability targets while also serving the increasing throughput and latency needs of applications.
* COREnext will develop a trustworthy-by-design architecture, which protects user privacy and platform integrity, while supporting 6G compute demands in edge servers, base stations, and client-side devices.
The work performed in the first 18 months followed a flow from use cases via requirements and a system architecture down to needed component advancements. This technical work is followed by a cadence of deliverables summarizing and contextualizing the achieved results. Main Achievements along this flow of work are:
* Use cases and scenarios were selected which would be used to guide the technical development. Requirements were formulated that will direct the validation of our achievements.
* From these requirements, an architecture for the project was defined, encompassing terminal devices, base stations, and edge cloud. Trustworthiness is considered from the start as a North Star for the technical design. From this architecture, necessary advancements beyond the state of the art are defined for individual key components.
* In particular, we identified four clusters of interacting components requiring innovation beyond the state of the art: efficient signal processing and acceleration, efficient interconnects, infrastructure authentication and attestation, and trusted digital computation.
These key components are now being developed and tested with initial results available. The second half of the project will then see a bottom-up iteration, where component results are used to refine the architecture and requirements are used to validate the delivered advancements beyond the state of the art.
Technical work within COREnext is organized in two orthogonal dimensions: digital and analogue as well as efficiency and trustworthiness. Within each of the four quadrants, the project develops qualitative and quantitative improvements beyond the state of the art:
* For efficient digital compute, we develop accelerators for selected steps of the signal processing chain, where energy savings are most critical. The relevant trade-off to be evaluated is chip area and related manufacturing costs against the gain in performance delivered per Watt of power. A qualitative improvement will be support for multi-tenancy for accelerators, improving on overall resource utilization.
* For trustworthy digital compute, we develop a trustworthy system-on-chip platform based on the M³ system architecture. The qualitative improvement will be the addition of low-complexity Trusted Execution Environments (TEEs). The relevant trade-off to be evaluated is the latency cost of the added hardware security primitives against the improved attack resilience of the system.
* In terms of analogue efficiency improvements, we have identified the cost of data movement across interconnects as a major source of energy consumption in base stations and edge clouds. For such networks, we are developing interconnect technology based on plastic fibres as communication waveguides. These low-cost fibres can deliver substantial benefits in terms of energy spent per transferred bit while also allowing low-latency and high-throughput connectivity.
* Because the analogue radio interface is the most exposed and thus hackable interface of the system, we need to improve its trustworthiness. We do so by developing radio fingerprinting as a method to identify valid participants using machine learning classification. This first-line-of-defense mechanism can help to prevent malicious devices from interfering with radio equipment. Accuracy and false positive rate are quantities we intend to evaluate.
While these components are being developed individually, they are all connected to an overall system architecture supporting our desired use cases. Validation against requirements from these use cases will occur in the second half of the project. All components are targeting TRL level 4, so further development is needed to achieve productization and final market impact.
* For efficient digital compute, we develop accelerators for selected steps of the signal processing chain, where energy savings are most critical. The relevant trade-off to be evaluated is chip area and related manufacturing costs against the gain in performance delivered per Watt of power. A qualitative improvement will be support for multi-tenancy for accelerators, improving on overall resource utilization.
* For trustworthy digital compute, we develop a trustworthy system-on-chip platform based on the M³ system architecture. The qualitative improvement will be the addition of low-complexity Trusted Execution Environments (TEEs). The relevant trade-off to be evaluated is the latency cost of the added hardware security primitives against the improved attack resilience of the system.
* In terms of analogue efficiency improvements, we have identified the cost of data movement across interconnects as a major source of energy consumption in base stations and edge clouds. For such networks, we are developing interconnect technology based on plastic fibres as communication waveguides. These low-cost fibres can deliver substantial benefits in terms of energy spent per transferred bit while also allowing low-latency and high-throughput connectivity.
* Because the analogue radio interface is the most exposed and thus hackable interface of the system, we need to improve its trustworthiness. We do so by developing radio fingerprinting as a method to identify valid participants using machine learning classification. This first-line-of-defense mechanism can help to prevent malicious devices from interfering with radio equipment. Accuracy and false positive rate are quantities we intend to evaluate.
While these components are being developed individually, they are all connected to an overall system architecture supporting our desired use cases. Validation against requirements from these use cases will occur in the second half of the project. All components are targeting TRL level 4, so further development is needed to achieve productization and final market impact.