Periodic Reporting for period 1 - EASIFeT (Energy-efficient Artificial Synapses based on Innovative Ferroelectric Transistors)
Reporting period: 2023-11-01 to 2025-10-31
The fast development and extensive use of powerful generative Artificial Intelligence models is causing a massive increase in the demand of computing power for data processing. The training of AI models, which often have billions of parameters, requires a staggering amount of electricity and comes with serious environmental consequences, including increased carbon dioxide emissions and water consumption, besides putting the electric grid under severe stress. Data centers already consume roughly 1.5% of global electricity, and the International Energy Agency predicts that this figure could double by 2030, reaching a level of consumption comparable to that of the entire country of Japan. This calls for a new way of designing computing systems to overcome the "bottleneck" of traditional computers, which physically separates the processing unit from the memory unit and forces data to constantly travel back and forth between the two, limiting the performance and energy efficiency of the entire system. A paradigm switch to data-centric platforms, with the co-localization of processing and memory functionalities, would be thus highly beneficial. Neuromorphic computing addresses this challenge by developing low-power computing chips that mimic the brain's structure, which leverages distributed computing in artificial neurons and localized storage in artificial synapses and drastically reduces the need for constant data transfer. Neuromorphic chips have the potentiality to not only reduce global energy consumption but also enable "edge computing", allowing mobile devices, medical sensors, and autonomous vehicles to process complex data directly on a local hardware, rather than relying on distant, power-hungry data centers. The development of highly energy efficient artificial synapses represents a crucial step for the realization of neuromorphic circuits. An artificial synapse is a nanoelectronic component designed to mimic the functions of a biological synapse, i.e. the connection between neurons. In the human brain, information is passed between neurons through a synapse: the strength of this connection is the synaptic weight. A strong weight means the signal passes easily, whereas a weak weight means the signal is nearly blocked. Thus, the most critical function of an artificial synapse is the ability to exhibit plasticity, meaning that the synaptic weight (usually electrical conductance) can be modulated by incoming electrical signals.
Among the different technological implementations of artificial synapses, ferroelectric devices are emerging as promising candidates due to their high energy efficiency and compatibility with standard CMOS circuit processing. Their development started with the recent European discovery of ferroelectricity in hafnium oxide. Ferroelectric materials, in particular hafnium zirconium oxide, contain microscopic electrical dipoles, due to the non centro-symmetric nature of the unit cell. Each dipole has two possible orientations, i.e. it can either “point up” or “point down”, and it can be flipped by an applied electric field, thus acting as a stable, non-volatile switch.
EASIFeT project investigated, by means of analytical and numerical simulations, a specific ferroelectric device, namely a Ferroelectric Schottky Barrier Field Effect Transistor (Fe-SBFET), as an artificial synapse for neuromorphic computing. This device is particularly interesting because it can be fabricated in the back-end-of-line (BEOL) of CMOS circuits (i.e. on top of standard chips with a 3D integration), and it features at least three terminals, thus making it possible to decouple write and read operations. The objectives of this study were: a) the development of a TCAD framework for the numerical simulation of such devices; b) the use of TCAD simulations to identify optimization strategies for energy efficient artificial synapses; c) the development of compact models for circuit-level simulation of the Fe-SBFETs.
Among the different technological implementations of artificial synapses, ferroelectric devices are emerging as promising candidates due to their high energy efficiency and compatibility with standard CMOS circuit processing. Their development started with the recent European discovery of ferroelectricity in hafnium oxide. Ferroelectric materials, in particular hafnium zirconium oxide, contain microscopic electrical dipoles, due to the non centro-symmetric nature of the unit cell. Each dipole has two possible orientations, i.e. it can either “point up” or “point down”, and it can be flipped by an applied electric field, thus acting as a stable, non-volatile switch.
EASIFeT project investigated, by means of analytical and numerical simulations, a specific ferroelectric device, namely a Ferroelectric Schottky Barrier Field Effect Transistor (Fe-SBFET), as an artificial synapse for neuromorphic computing. This device is particularly interesting because it can be fabricated in the back-end-of-line (BEOL) of CMOS circuits (i.e. on top of standard chips with a 3D integration), and it features at least three terminals, thus making it possible to decouple write and read operations. The objectives of this study were: a) the development of a TCAD framework for the numerical simulation of such devices; b) the use of TCAD simulations to identify optimization strategies for energy efficient artificial synapses; c) the development of compact models for circuit-level simulation of the Fe-SBFETs.
Research activities in EASIFeT involved the development and calibration to experimental data of TCAD set-ups for the different sub-blocks of the full device, the ferroelectric layer, the Schottky contacts, the traps at interfaces and in dielectrics, and channel semiconductor material in the channel of the Fe-SBFETs. Full TCAD workflows for the Fe-SBFET, for different device architectures, in 2D and 3D, and using different ferroelectric models have been then realized. These simulation set-ups enabled us to investigate how different device designs and operating conditions affect the device performance.
Optimization strategies regarding the device architectures and materials have been derived. In particular, it has been shown that the integration of a metal interlayer in the gate stack, in between the ferroelectric and the dielectric layers, alleviates the dependence of the device operation on charge trapping. In fact, in ferroelectric devices, the switching of the ferroelectric polarization is tightly correlated to high density of traps in the dielectric stack: charge trapping reduces the ferroelectric depolarization field by partly compensating the ferroelectric polarization, thus stabilizing the polarization. The ferroelectric devices operation is therefore inherently linked to traps, which cannot be easily engineered and thus cannot be considered an actual design option. The charge in the metal interlayer, having opposite sign with respect to the polarization, can effectively reduce the depolarization fields, thus disentangling ferroelectric stabilization from the density of traps in the gate stack. The charge in the metal interlayer, injected by tunneling from the semiconductor through the dielectric layer, can be more easily engineered compared to the trapped charge, for example by properly designing the voltage pulses applied at the gate and the composition and the thickness of the dielectric layer. Moreover, simulations have shown that, by injecting different charge levels in the metal interlayer, it is possible to obtain a multilevel operation even for highly scaled devices exhibiting a two-level or a very-few-level polarization behavior.
Next, the amenability of the Fe-SBFETs as artificial synapse has been investigated by simulating the synaptic functionality. The analysis began with the basic excitatory post-synaptic current (EPSC) response, namely by simulating how the Fe-SBFET output current changes after an input voltage signal, or “spike,” is received. Then, long-term potentiation and depression in the synaptic strength were simulated by applying repeated voltage pulses to the device. It was observed that the synaptic strength can be gradually increased or decreased depending on the number of pulses. Also Spike-timing dependent plasticity (STDP), a biologically plausible learning rule, whereby the change in synaptic strength is determined solely by relative timing of spikes at the presynaptic and postsynaptic neurons, could be successfully implemented in the Fe-SBFET. Finally, a compact model for SPICE-compatible circuit simulations of ferroelectric-modulated Schottky junctions has been developed and implemented in Verilog-A language, which is a hardware description language and the de facto standard language used in the semiconductor industry for the implementation of compact models.
Optimization strategies regarding the device architectures and materials have been derived. In particular, it has been shown that the integration of a metal interlayer in the gate stack, in between the ferroelectric and the dielectric layers, alleviates the dependence of the device operation on charge trapping. In fact, in ferroelectric devices, the switching of the ferroelectric polarization is tightly correlated to high density of traps in the dielectric stack: charge trapping reduces the ferroelectric depolarization field by partly compensating the ferroelectric polarization, thus stabilizing the polarization. The ferroelectric devices operation is therefore inherently linked to traps, which cannot be easily engineered and thus cannot be considered an actual design option. The charge in the metal interlayer, having opposite sign with respect to the polarization, can effectively reduce the depolarization fields, thus disentangling ferroelectric stabilization from the density of traps in the gate stack. The charge in the metal interlayer, injected by tunneling from the semiconductor through the dielectric layer, can be more easily engineered compared to the trapped charge, for example by properly designing the voltage pulses applied at the gate and the composition and the thickness of the dielectric layer. Moreover, simulations have shown that, by injecting different charge levels in the metal interlayer, it is possible to obtain a multilevel operation even for highly scaled devices exhibiting a two-level or a very-few-level polarization behavior.
Next, the amenability of the Fe-SBFETs as artificial synapse has been investigated by simulating the synaptic functionality. The analysis began with the basic excitatory post-synaptic current (EPSC) response, namely by simulating how the Fe-SBFET output current changes after an input voltage signal, or “spike,” is received. Then, long-term potentiation and depression in the synaptic strength were simulated by applying repeated voltage pulses to the device. It was observed that the synaptic strength can be gradually increased or decreased depending on the number of pulses. Also Spike-timing dependent plasticity (STDP), a biologically plausible learning rule, whereby the change in synaptic strength is determined solely by relative timing of spikes at the presynaptic and postsynaptic neurons, could be successfully implemented in the Fe-SBFET. Finally, a compact model for SPICE-compatible circuit simulations of ferroelectric-modulated Schottky junctions has been developed and implemented in Verilog-A language, which is a hardware description language and the de facto standard language used in the semiconductor industry for the implementation of compact models.
They key results are a detailed analytical and numerical modeling of the ferroelectric transistors featuring Schottky barriers, which lead to the development of dedicated TCAD workflows and the derivation of guidelines for the design and fabrication of more efficient artificial synapses for neuromorphic computing, and the development of a Verilog-A compact model for circuit simulation of such devices.