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Parallel Architectures and Languages for AIP:a VLSI-Directed Approach

Objective

PALAVDA was launched to study the performance of different approaches to symbolic processing on parallel architecture computers as a step towards establishing a European standard for a generic architecture for logic, functional and object-oriented languages.
The project aimed to investigate different non von-Neuman architectures and to implement some of them. The prime objective was to reduce the execution times required by AI applications by a substantial factor. Concurrency was to be achieved through a large number of identical processing elements implemented in VLSI. Ideally, a concurrent machine should support all three programming styles (object-oriented, functional and logic), which will allow the full exploitation of concurrency, but the principles upo n which such a machine could be based are not yet fully understood. All three styles were to be explored through studies of machines which support each programming style separately, and through common working groups which were to explore several areas of general relevance.
The project was divided into a series of subprojects:
-A, where the relation between an object-oriented style with active and passive objects and a highly parallel architecture was investigated and developed. The parallel architecture typically contained up to 1024 Processor/Communication Modules (PCMs). Th ree applications (a natural language translator, a knowledge-based system and a multi-level VLSI simulator) were implemented on the machine.
-B, where the relation between a functional style and a highly paralleled architecture was investigated. Here the approach was how a paralleled reduction machine could be supported by up to 10 000 PCMs.
-C, where the relation between a logic programming style and a highly parallel architecture was studied. The approach here was how a parallel inference machine could be supported by PCMs.
-D, where the relation between a mixed logic and functional style and a highly parallel architecture was studied. Here, the algorithmic parts of an application were to be handled within the functional part, while the non-deterministic (inferential) parts were treated within the logical subset of the language. This improved efficiency. Of course, an important point was the relation between the semantics of functional and logic styles. The question was again how this style could be supported by PCMs.
-E, where the relation between functional programming and data-flow was investigated. The approach was to study how the data-flow machine could be structured from about 100 PCMs and supported by a high-level application language.
-F, which addressed the three main styles of new generation programming:functional, parallel and logic. The long-term objective was to arrive at a VLSI implementation of a highly parallel inference machine. On the way to that objective the connection method was to be used.
All the subprojects were based on messages passed between identical units (PCMs), consisting of communication hardware, processing hardware and local memory. In addition to the subprojects, an application study group was formed to select applications withwhich the various styles might be evaluated and their suitability for various fields of application established.
The parallel multilevel simulator (PMLS) for very large scale integration (VLSI) circuits runs on general purpose parallel machines and combines multilevel simulation and exploitation of parallelism on the circuit level (ie distributed discrete event simulation using circuit partitioning) to achieve high performance. The parallel multilevel simulator is, to our knowledge, the first general purpose parallel multilevel simulator for very large scale integration circuits. It provides high flexibility (due to object oriented programming) and a highly interactive user interface including zooming (ie dynamic change of the abstraction level).

The parallel fault simulator (PFS), running on a local area network (LAN), divides a set of faults into subsets which are then processed as parallel tasks in the network processors. A control process controls the execution processors and gathers and analyses the results. The use of local area networks accelerates fault simulation.

The project was intended to study the performance of different approaches to symbolic processing on parallel architecture computers as a step towards establishing a European standard for a generic architecture for logic, functional and object oriented languages. The project aimed to investigate different non-von Neuman architectures and to implement some of them. The prime objective was to reduce the execution times required by artificial intelligence (AI) applications by a substantial factor. Concurrency was achieved through a large number of identical processing elements implemeted in very large scale integration (VLSI). Ideally, a concurrent machine should support all 3 programming styles (object oriented, functional and logic), allowing the full explitation of concurrency. Firstly, the relation between an object oriented style with active and passive objects and a highly parallel architecture was investigated. A parallel object oriented language POOL has been designed and implented. Two semantics, proved equivalent, were developed for POOL: denotational and operational. A 100 node prototype, POOMA, has been developed. Each node consists of a processor, a memory, and a communication processor designed in the project. It exhibits 200 Mips, 10 Mflops, 1.6 Gbyte main memory, 15 Gbyte background memory and 1 Gbyte/s communication bandwidth. An operating system has been developed for POOMA. Various applications were developed, the most advanced one being a parallel VLSI simulator. Secondly, the relation between a functional style and a highly parallel architecture was examined. The results are mainly theoretical. A parallel evaluation model for functional languages has been designed and implemented on a network of transputers. Thirdly, the relation between a logic programming style and a highly parallel architecture was investigated. The major contribution was the development of the Alexander method and its execution model. This allows the merging of recursive and non recursive views in queries. The execution model was implemented in a twin SPS7 multiprocessor architecture with good performance results. Fourthly, the relation between a mixed logic and functional style and a highly parallel architecture was studied. A language called IDEAL, which subsumes Prolog and functional languages, has been designed and implemented. The speedup obtained shows real performance improvements via parallelism over the best sequential technology. Fifthly, the relation between functional programming and dataflow was examined. A data flow language has been designed and a 4 node data flow multiprocessor machine constructed, together with an operating system and a language. The machine was experimented on with database applications. Sixthly, use of the connection method to integrate cell 3 styles of programming. The major results concern the field of theorem proving, where a sequential and a parallel theorem prover based on the connection method have been implented. A functional parallel language, FP2, was used to specify the provers.
A
Results fall mainly into three categories:
-Language
A parallel object-oriented language POOL has been designed and implemented. Two semantics, proved equivalent, were developed for POOL: denotational and operational.
-Hardware and System Software
a 100 node prototype, POOMA, has been developed. Each node consists of a processor, a memory, and a communication processor designed in the project. It exhibits 200 Mips, 10 Mflops, 1.6 Gbyte main memory, 15 Gbyte background memory and 1 Gbyte/s communic ation bandwidth. An operating system has been developed for POOMA.
-Application
Various applications were developed, the most advanced one being a parallel VLSI simulator.
B
The results are mainly theoretical. A parallel evaluation model for functional languages has been designed and implemented on a network of transputers.
C
The major contribution was the development of the Alexander method and its execution model. This allows the merging of recursive and non-recursive views in queries. The execution model was implemented in a twin SPS7 multiprocessor architecture with good performance results.
D
A language called IDEAL, which subsumes PROLOG and functional languages, has been designed and implemented on the PIPE parallel transputer machine developed in project 26. The speed-up obtained shows real performance improvements via parallelism over the best sequential technology.
E
A data-flow language has been designed and a four-node data-flow multiprocessor machine constructed, together with an operating system and a language. The machine was experimented on with database applications, and the performances obtained are promising.F
The major results concern the field of theorem-proving, where a sequential and a parallel theorem-prover based on the connection method have been implemented. A functional parallel language, FP2, was used to specify the provers.
On the whole, the project has shown the crucial importance of compilation techniques and the importance of getting the "grain to communication" ratio right for the application. Several books and numerous scientific papers have been published on the various aspects of the project.
Exploitation
The PALAVDA project has played an important role in the scientific progress of parallel computer systems for symbolic and advanced information processing in the past five years. Through its broad scope, covering the dominant programming styles and the entire spectrum of system and application design, it has been able to contribute to the advances in various fields and disciplines that together are needed to design a parallel computer.
Finally, PALAVDA has largely contributed to the fact that Europe now has a large number of experienced researchers and system designers in the area of symbolic parallel computer systems.
The results of the project will provide a solid basis for a variety of more development-oriented projects.

Coordinator

Philips GmbH
Address
Theodor-heuss-allee 106
60486 Frankfurt Am Main
Germany

Participants (5)

Bull SA
France
Address
68 Route De Versailles
78430 Louveciennes
Centro Studi e Laboratori Telecomunicazioni SpA
Italy
Address
Via G. Reiss Romoli, 274
10148 Torino
DAIMLER-BENZ AG
Germany
Address
Hollanderstraße
1000 Berlin
GEC-Marconi Materials Technology Ltd
United Kingdom
Address
Elstree Way
WD6 1RX Borehamwood
Siemens Nixdorf Informationssysteme AG
Germany
Address
Pontanusstraße 55
33102 Paderborn