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A Preliminary Study of a Vector Processing-Oriented Parallel Architecture

Objective

This project was a preliminary study of a vector oriented-processing parallel architecture for a supercomputer. It combined a user and a technological approach. Its two objectives were:
-To define, with the help of some qualified users, the architectural concepts for a high performance scientific and numeric supercomputer working in the 10-30 Gflops range. Compatibility with existing programs and applications was a major criterion.
-To evaluate the defined architecture by simulations at the hardware and software levels. The different technologies available to develop this type of machine were analysed (eg circuits, memories, interconnections, packaging, cooling), with reliability a nd maintainability two of the main criteria for selection.
This project was a preliminary study of a vector oriented processing parallel architecture for a supercomputer. It combined a user and a technological approach. Its 2 objectives were: firstly, to define, with the help of some qualified users, the architectural concepts for a high performance scientific and numeric supercomputer working in the 10 to 30 Gflops range. Compatibility with existing programs and applications was a major criterion. Secondly, to evaluate the defined architecture by simulations at the hardware and software levels. The different technologies available to develop this type of machine were analysed (eg, circuits, memories, interconnections, packaging, cooling), with reliability and maintainability 2 of the main criteria for selection. A study of the needs of 25 users for applications software, basic software and hardware was made, and the product choice criteria examined. An evaluation was carrried out of the application of different types of architecture to several fields. The existing technologies (integrated processors and memory chips) were studied, and trends extracted. Pre-studies of a metal oxide semiconductor (MOS) chip for 15 ns, 64 bit processors and a 60 Mips scalar processor were made. A study of a very high speed ring system was performed. Different FORTRAN programming methods usable in parallel processing tasks were studied.
Results were as follows:
-a study of the needs of 25 users for applications software, basic software and hardware was made, and the product choice criteria examined
-an evaluation was carried out of the application of different types of architecture to several fields
-the existing technologies ( integrated processors and memory chips) were studied, and trends extracted
-pre-studies of a MOS chip for 15 ns, 64-bit processors and a 60 Mips scalar processor were made
-a study of a very high-speed ring system was performed
-different FORTRAN programming methods usable in parallel processing tasks were studied.
Exploitation
This study allowed the partners to identify the need to develop high-performance computers, an area where Europe is very weak.

Coordinator

Bull SA
Address
Tour Bull 1 Place Carpeaux Puteaux
92039 Paris La Défense
France

Participants (1)

Siemens Nixdorf Informationssysteme AG
Germany
Address
Otto-hahn-ring 6
81739 München