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Content archived on 2024-04-15

Substrates for CMOS VLSI Technology

Objective

The objectives of this project were to:
1.Set up an intrinsic gettering (IG) process for wafers with medium to high oxygen concentration. The process was to have been independent of the type (porn) of the substrate and able to produce a highly defective bulk region and a defectfree denudedzone. A zone thickness of around 110micron was identified as the best compromise for several factors (such as leakage current and insensitivity to latch up a soft error).
2.Characterise EPI wafer diameters of 4 and 6inches. The thickness of the epilayer was to have been in the range 510micron, for both p+ and n+substrates. This thickness range is suitable for submicron CMOS. Finally, IG and EPI processes were eventually to match in order to have intrinsically gettered, low-leakage EPI wafers for submicron CMOS devices insensitive to soft errors.
The objectives of this project were to:
set up an intrinsic gettering (IG) process for wafers with medium to high oxygen concentration;
characterise energy and process integration (EPI) wafer diameters of 4 and 6 inches;
Initial work was carried out on both the correlation between intrinsic defects, processes and device electrical performance, and also in the area of self interstitials (injected by oxygen precipitation and by source to drain ion implantation) as a cause of leakage and lifetime degradation. The final area of work addressed by the project was the design of the preaneal process to match the desired defectiveness and lifetime characteristics.
Problems in the supply of EPIwafers caused delays the first year. This situation improved in the second year, and some of the main targets were achieved at the end of the two-year contract. Initial work was carried out on both the correlation between int rinsic defects, processes and device electrical performance, and also in the area of self-interstitials (injected by oxygen precipitation and by sourcetodrain ion implantation) as a cause of leakage and lifetime degradation.
The final area of work addressed by the project was the design of the pre-anneal process to match the desired defectiveness and lifetime characteristics.

Topic(s)

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Call for proposal

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Funding Scheme

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Coordinator

Thomson Microelectronics Srl (SGS)
EU contribution
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Address
Via Carlo Olivetti
20041 Agrate Brianza Milano
Italy

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Total cost
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Participants (2)