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Silicon-on-Insulator Materials and Processing: Towards 3-D Integration

Objective

The objective was to investigate new silicon technologies suitable for 3-D integration in order to achieve higher density integration, higher speed of operation and multifunctional signal processing. Three main technological steps were explored:
-the growth of SOI active layers with electronic properties needed for the realisation of high quality devices and circuits
-the stacking of two active levels in a way that avoids any degradation of already built devices
-single-level SOI processing for the fabrication of individual components and for their connection, and the development of a process incorporating two active layers.
A final demonstration was presented during the ESPRIT Conference in November 1988.
The objective was to investigate new silicon technologies suitable for 3-dimensional integration in order to achieve higher density integration, higher speed of operation and multifunctional signal processing. 3 main technological steps were explored:
the growth of silicon on insulator (SOI) active layers with electronic properties needed for the realisation of high quality devices and circuits;
the stacking for 2 active levels in a way that avoids any degradation of already built devices;
single level SOI processing for the fabrication of individual components and for their connection, and the development of a process incorporating 2 active layers.

High quality SOI devices have been produced, and fine geometry bulk complementary metal oxide semiconductor (CMOS) devices which had undergone SOI recrystallisation were found to be essentially unaffected by the procees. These device results confirm the viability of the demonstrator production technique. Full demonstrator device batches were processed. A working chip, integrated in a prototype board and activating a stepper motor, was shown.

The chosen demonstrator is a first step towards the integration of very different functions on the same chip in a way which allows, simultaneously, the independent optimisation of each function and their complete dielectric isolation, thus opening the route for complex 3-dimensional system integration on chips, allowing more reliability and better performance.
The first two years' experimental work demonstrated the capacity to fabricate monocrystalline SOI layers compatible with the underlying bulk silicon layers and with limited influence of the first device level on the SOI characteristics. Specifically:-industrial E-beam equipment was built for SOI preparation, and two different research laser systems were optimised
-unified test structures and characterisation methods were adopted for quantitative comparison of the crystallisation techniques of E-beam, laser zone melting and CVD epitaxy.
In parallel, design options and product application studies showed two possible choices for 3-D circuits:
-conventional applications (high-density high-performance VLSI)
-system applications (specialised superimposed layers and performance-independence of different functions).
One major conclusion of the application study was that 3-D SOI CMOS for VLSI is unlikely to provide sufficient benefit, in terms of packing density and circuit speed, to compete with single-level technologies using bulk or SOI substrates. In contrast, thedevelopment of silicon technologies, where devices of different types (eg CMOS, bipolar and power transistors) can be fabricated on a single chip, was demonstrated as an important application area for 3-DSOI. Such mixed technologies are difficult to produce in a single level of silicon, as the requirements of the different device types often conflict. However, using a 3-D SOI approach, the development of a mixed technology with individual optimisation of the separate device levels can be envisaged.In the light of these findings the orientation of the project and the end of the year 3demonstrator was focused on the development of a "smart power" technology using a 3micron CMOS SOI level to control medium current/voltage (1 A/50 V) LDMOS bulk transistors. The particular application considered was a stepper motor controller using a gate array design approach for both the CMOS and LDMOS levels. A "mezzanine" layout was adopted whereby the SOI devices are displaced laterally from the underlying bulk devices.
On the materials development side, significant improvements in the SOI starting material, especially the use of selective epitaxial growth of silicon in the seed windows, together with refinements of the laser and electron beam recrystallisation systems, have allowed the production of device-grade SOI compatible with the requirements of the end of project demonstrator. High-quality SOI devices have been produced, and fine geometry bulk CMOS devices which had undergone SOI recrystallisation under similar c onditions were found to be essentially unaffected by the process. These device results confirm the viability of the demonstrator production technique. Full demonstrator device batches were processed in December1987. A working chip, integrated in a protot ype board and activating a stepper motor, was shown during the ESPRIT Conference in November1988.
Exploitation
The chosen demonstrator is a first step towards the integration of very different functions on the same chip in a way which allows, simultaneously, the independent optimisation of each function and their complete dielectric isolation, thus opening the route for complex 3-D system integration on chips, allowing more reliability and better performance.

Coordinator

SGS Thomson Microelectronics SA
Address
17 Avenue Des Martyrs
38340 Grenoble
France

Participants (5)

Centre National d'Études des Télécommunications (CNET)
France
Address
98 Chemin Du Vieux Chêne
38243 Meyland
Commissariat à l'Energie Atomique (CEA)
France
Address
Centre D'études De Grenoble 17 Avenue Des Martyrs
38041 Grenoble
GEC-Marconi Materials Technology Ltd
United Kingdom
Address
Elstree Way
WD6 1RX Borehamwood
NATIONAL MICROELECTRONICS RESEARCH CENTRE
Ireland
Address
Prospect Row
X Cork
THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
United Kingdom
Address
Wilberforce Road
CB3 0WB Cambridge