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Wafer-Scale Integration

Objective

The objective of project 824 was to use the Wafer-Scale Integration (WSI) approach to build systems of up to 25million transistors on a 4" wafer using a hierarchical approach to implement tolerance to end-of-manufacturing defects. Progress was to be embo died in three demonstrators:
-4.5Mbit Static RAM
The main goal of the 4.5Mbit RAM memory (access time 100ns) was to check the possibility of using switches efficiently in order to discard faulty elements and replace them with spares. Starting from cells of 64Kword of 1bit, the final interconnectionnetwork, produced on a 4"wafer, implemented 18blocks of 256Kx1bit.
-WSI Systolic Array
Systolic arrays are well suited to WSI because all communications are between nearest neighbours. The approach taken was to define a general-purpose architecture that was likely to cope with many application problems, notably in processing video images,display graphics and advanced memory devices. The chosen architecture is a 128x128array of processing elements.
-16-bit Microprocessor
The long-term goal was to integrate a fully dedicated system on a single chip using pre-defined blocks embedded in a flexible interconnection structure (a sea of gates, for instance). Being the master block of the system and one of the biggest ones, themicroprocessor had to be particularly adapted to the application, but its architecture had also be compatible with fault tolerance. The project aimed to develop a library of pre-defined and parametrised elements as well as design tools to produce the layout of a 16-bit reconfigurable microprocessor. Such an approach is needed in order to guarantee short design times together with adaptation to the application constraints in both terms of functionality and speed.
The objective of project 824 was to use the wafer scale integration (WSI) approach to build systems of up to 25 million transistors on a 4 inch wafer using a hierarchical approach to implement tolerance to end of manufacturing defects. Progress was to be embodied in 3 dimenstrators:
4.5 Mbit static random access memory (SRAM);
WSI systolic array;
16-bit microprocessor.

The first silicon (WSI test mask) on wafer scale integration was processed successfully. Switches to reconfigure a wafer were dispatched to every partner; either to blow the fuse, to correct with laser lithography and lift off or to charge and discharge floating gate field effect transistors (FET). The first results on the characterisation of these switches are in agreement with the target.

Blocks for building the wafer scale demonstrators were designed and processed with:
16 + 1 spare bit application specific microprocessor (building block for a big chip with microprocessor, memory, peripherals, etc);
2 x 2 and 8 x 8 systolic arrays (building blocks for a wafer scale systolic array);
extra hardware necessary to interconnect on wafer 72 static RAM of 64 Kword x 1 bit, in order to achieve a 4.5 Mbits SRAM.
Additionally, 2 WSI architectures, for a memory and a systolic array, have been proposed with solutions to the difficult problem of reconfiguration and testability. The current work consists of fabrication and test of the systolic array wafer.
The operating environment is as follows :
Computer aided design (CAD) and design methodologies/silicon technologies and packaging
During the first year, the first silicon (WSI test mask) on Wafer Scale Integration was processed successfully. Switches to reconfigure a wafer were dispatched to every partner; either to blow the fuse, or to correct with laser lithography and liftoff, o r to charge and discharge floating-gate FETs. The first results on the characterisation of these switches are in agreement with the target.
Blocks for building the wafer-scale demonstrators were designed and processed during the second year:
-16+1spare bit application-specific microprocessor (building block for a "bigchip" with microprocessor, memory, peripherals, etc )
-2 x 2 and 8 x 8 systolic arrays (building blocks for a wafer-scale systolic array)
-extra hardware necessary to interconnect on wafer 72static RAM of 64Kword x 1bit, in order to achieve a 4.5MbitsSRAM.
Additionally, two WSI architectures, for a memory and a systolic array, have been proposed with solutions to the difficult problem of reconfiguration and testability. The current work consists of fabrication and test of the systolic array wafer.
Exploitation
The developed know-how in technology will allow correction of end-of-manufacturing defects and hence improve the ability to realise full custom, one million transistor chips for the ASIC sector.
From the system point of view, the developed systolic array, as it is more compact and can contain more processors than any other available system, is opening up a whole new range of uses, notably for signal processing functions in video applications.

Coordinator

SGS Thomson Microelectronics SA
Address
17 Avenue Des Martyrs
38340 Grenoble
France

Participants (5)

British Telecom plc (BT)
United Kingdom
Address
British Telecom Laboratories Martlesham Heath
IP5 7RE Ipswich
Commissariat à l'Energie Atomique (CEA)
France
Address
Centre D'études De Grenoble 17 Avenue Des Martyrs
38041 Grenoble
Institut National Polytechnique de Grenoble
France
Address
46 Avenue Félix Viallet
38031 Grenoble
NATIONAL MICROELECTRONICS RESEARCH CENTRE
Ireland
Address
Prospect Row
X Cork
Technische Hochschule Darmstadt
Germany
Address
Schloßgartenstraße
64289 Darmstadt