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Advanced Interconnect for VLSI

Objective

The objective of this project was to develop high density interconnect compatible with one micron MOS and bipolar VLSI technologies. This technology was to feature four levels of low resistivity metal interconnect with high electromigration resistance andstable, low-resistance contacts to the underlying silicon circuit.
The objective of this project was to develop high density interconnect compatible with one micron metal oxide semiconductor (MOS) and bipolar very large scale integration (VLSI) technologies. This technology was to feature 4 levels of low resistivity metal interconnect with high electromigration resistance and stable, low resistance contacts to the underlying silicon circuit. The project achieved its overall objectives and demonstrated several advanced new techniques. The main milestones of the programme were:
demonstration of 3-layer metal at 5 micron pitch;
demonstration of 4-layer metal at 3 micron pitch.
The first main milestone was reached and several variants of the developed structures for nonnested vias and pillars were evaluated by means of the final test mask.
The fabrication of 100 per cent filled small vias with aluminium alloys was eventually demonstrated. Work on contact systems and tests on the reliability of polyamide and nitride produced very good results.
The project achieved its overall objectives and demonstrated several advanced new techniques.
The main milestones of the programme were:
-demonstration of 3layer metal at 5micron pitch (September1986)
-demonstration of 4-layer metal at 3micron pitch (March1987).
The first main milestone was reached on time and several variants of the developed structures for non-nested vias and pillars were evaluated by means of the final test mask towards the final milestone.
A major technical difficulty was encountered while setting up the final process. Although good progress had been made with optimised aluminium for step coverage, it was discovered that these conditions did not fill small holes such as contacts and vias. The work was therefore restructured and new sub-tasks added in order to reach the final milestone. The fabrication of 100% filled small vias with Al alloys was eventually demonstrated following close collaboration with advanced equipment manufacturers.Work on contact systems and tests on the reliability of polyimide and nitride also produced very good results.
Exploitation
All the partners make use of the developed interconnect results in their CMOS or bipolar processes. Plessey, notably, has transferred the 3layer metallisation scheme developed to its CMOS process.

Coordinator

GEC Plessey Semiconductors plc
Address
Caswell
NN12 8EQ Towcester
United Kingdom

Participants (3)

GEC-Marconi Materials Technology Ltd
United Kingdom
Address
Elstree Way
WD6 1RX Borehamwood
Telefunken Microelectronic GmbH
Germany
Address
Theresienstraße 2
74072 Heilbronn
Thomson CSF
France
Address
38 Rue Vauthier
92100 Boulogne-billancourt