Exploitable results
The integrated NODE project is developing and evaluating technologies for growth and processing of semiconductor nanowire devices for their possible impact as key add-on technologies to standard semiconductor fabrication. The partners in NODE work on generating a deepened understanding of the physics phenomena of one-dimensional semiconductor materials and nanowire-based devices, and on developing new functionalities not found in traditional higher-dimensional device structures.
Materials growth and processing technologies of semiconductor nanowire devices will be developed and evaluated for their possible impact as key add-on technologies to standard semiconductor fabrication. The goal is also to reach a deepened understanding of the physics of one-dimensional semiconductor materials and nanowire-based devices, and to develop new functionalities not found in traditional higher-dimensional device structures.
NODE will study in detail a set of key device families based on semiconductor nanowires, such as tunnelling devices, and field-effect transistors, as well as explore unique opportunities that may be offered by nanowires in areas for storage applications. NODE will also make a dedicated effort to evaluate the potential for integration of nanowire-specific processing methods and to assess the compatibility with requirements from conventional semiconductor processing, as well as evaluate novel architectural device concepts and their implementation scenarios. More specifically the main objectives of NODE are to build and evaluate electronic devices based on semiconductor nanowires andto assess nanowire growth and related nanostructuring in terms of up-scalability and Si-integration potential.
The research in NODE in many cases represents the state-of-the art in its field. The NODE partners are currently in the research forefront in areas such as (i) understanding of nanowire growth mechanisms, (ii) control of nanowire growth and nanowire doping (iii) characterization of the structural properties of nanowires (iv) processing of vertical nanowires structures (v) device research and development along the two tracks: InAs nanowire wrap-gate FETs and Si nanowire tunnel FETs, using both etched (fully-CMOS compatible) and bottom-up grown nanowires.
Since the project includes partners with strong background in research related to CMOS-integration, NODE had a strong focus on finding CMOS-compatible growth methods and processing conditions. Important sub-projects have therefore been to develop growth methods where gold is not required, and catalyst-free techniques have been developed for both InAs- and Si-nanowires, and Al, Pd, Ag seeding of Si nanowires has been demonstrated. A particular effort was also made on investigating the effect of gold on Si nanowires during growth and processing.
Design, fabrication and characterization of the first reported vertical RF-compatible nanowire transistors were carried out, demonstrated with InAs wrap-gate nanowires. Steep slope devices based on Si-nanowires were implemented, where also the first functional Si nanowire tunnel-FETs processed on 200mm wafers on a CMOS platform were demonstrated. Finally, multi-gated Si nanowire Schottky barrier FETs were realized, where an inverter function was demonstrated.
The NODE project has had a very high output in publications, and in total over 100 articles has been published at the end of the project. This clearly shows that considerable progress was made in the project and that the research was competitive on an international level. The NODE partners have applied for at least 48 patents related to nanowire research and development, not including patent applications submitted within the last 18 months that are not yet publicly posted.
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