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High-Level CAD for Interactive Layout and Design

Objective

The objective of this project was to define and demonstrate a CAD system for the design and layout of VLSI integrated circuits from the initial specification to the masks. Circuit complexity up to 1 million transistors was to be addressed. Reduced design times were the overall aim. The main topics under investigation included high-level design methodology based on Petri nets, hierarchic floorplanning with a high degree of automation, analogue and general cell design, data modelling and database management.
The objective of this project was to define and demonstrate a computer aided design (CAD) system for the design and layout of very large scale integration (VLSI) integrated circuits from the initial specification to the masks. Circuit complexity up to 1 million transistors was to be addressed. Reduced design times were the overall aim.

A prototype system has been produced which allows a specification to be expressed as a Petri net as input and produces mask tapes as output. It incorporates a design methodology for analogue cells which has circuit performance optimisation properties.
The system features a sophisticated interface to the circuit level simulation package and is technology independent in its application.

Another major accomplishment was the verification of the operation of a multicache bus system by proving the correctness of the marking graph of its model.

The data requirements of each tool of the CAD system have been defined. A data model, which is adequate for the relational database management system (DBMS) of the design system, has been established. A graphic representation, which shows both how the attributes are associated to the relations and the access mechanism, has been established. Software for placement of general cells has been developed. A simulated annealing placement improver has also been developed.

Overall, the project has achieved its stated objectives in terms of the design and production of a CAD design. Validation of its performance, however, has not been demonstrated. The feasibility of describing systems using the Petri net notation and the fact that this can be automatically translated into circuits and layout has been demonstrated. This translation can substantially reduce the design time for complex chips.
The operating environment is as follows :
Computer aided design (CAD) and design methodologies
A prototype system has been produced which allows a specification to be expressed as a Petri-net as input and produces mask tapes as output. The prototype has the following features:
-It incorporates a design methodology for analogue cells which has circuit performance optimisation properties.
-The system features a sophisticated interface to the circuit-level simulation package and is technology-independent in its application. Tests of the system demonstrated its efficiency. The work-on-design rule independent description of cells has been co mpleted. A translation procedure from a physical into a symbolic description of cells and back into a different physical representation has been described. The elaborated method has been applied to both NMOS, CMOS and bipolar circuit examples.
-Another major accomplishment was the verification of the operation of a multi-cache bus system by proving the correctness of the marking graph of its model. This model was described by means of high-level Petri nets (RTPN) and proved by using a methodol ogy that permits a fast formal verification in place of the more usual slow simulation. Unfolding of the RTPN to an ordinary Petri net then leads to a correct and easy (one-to-one) hardware synthesis.
-The final revision of the design manual of 200 pages in length has been carried out entitled: "Design of digital systems using Petri nets". It contains all the important results on the design methodology.
-The data requirements of each tool of the CAD system have been defined. A data model, which is adequate for the relational DBMS of the design system, has been established in a close liaison between the project partners. A graphic representation, which s hows both how the attributes are associated to the relations and the access mechanism, has been established.
-Software for placement of general cells has been developed. It is based on constructive initial placement, using a mixture of rules and algorithms. A simulated annealing placement improver has also been developed. This software has been tested in a vari ety of technologies. The software has been integrated with the Oracle Database Management System on Apollo workstations, and with the Plessey MEGACELL Database Management System on DEC VAX. Studies have been made of the impact on future placement softwareof the power routing and hierarchy problems anticipated in future generations of technology.
Overall, the project has achieved its stated objectives in terms of the design and production of a CAD design. Validation of its performance, however, has not been demonstrated.
The feasibility of describing systems using the Petri-net notation and the fact that this can be automatically translated into circuits and layout has been demonstrated. This translation can substantially reduce the design time for complex chips.
The work on analogue circuits carried out has also made a valuable contribution to the state-of-the-art knowledge in this area, the more so as analogue in combination with digital functions on the same chip is gaining in importance.

Coordinator

GEC-Marconi Materials Technology Ltd
Address
Elstree Way
WD6 1RX Borehamwood
United Kingdom

Participants (3)

BULL SA
France
Address
Avenue De Malakoff
75116 Paris
Daimler-Benz AG
Germany
Address
Wilhelm-runge-straße 11
89013 Ulm
GEC Plessey Semiconductors plc
United Kingdom
Address
Caswell
NN12 8EQ Towcester