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Content archived on 2024-05-29

IP Core and System Design of Associative Memory Arrays for Semantic Search


Due to the enormous increase in stored digital content, any IT device must provide effective and intelligent search-retrieval functionality. Today, in order to retrieve a few relevant KB from a large digital store one moves in and out several (hundred) GB between memory and processor over a restricted size band bus. The only long-term solution is to delegate this task where it belongs: to the storage medium itself. By supporting at hardware level simple micro-operations performed in parallel, the AMASS project will provide a hardware platform for error tolerant storage and retrieval of electronic objects described by a set of binary features. The encoding and decoding of objects into/from binary features is performed externally on a general-purpose machine using current SW tools. This unified approach applies to different data structures, ranging from new and current storage technologies up to application-oriented solutions for database retrieval, ontology based intelligent internet components, and multimedia storage management. The main goal of the project is to develop the HW/SW intellectual property cores for implementing a general-purpose associative dynamic memory for storing and retrieving binary feature descriptors in Silicon platforms. This includes creating the general IP- and system framework. Beyond developing an abstract model supporting sophisticated pattern recognition and search tasks, the projects also targets a system design approach for a few concrete application fields. The targeted demonstrator is a content-based text retrieval system. It includes the corresponding IP cores methodology, the system software, and the middleware resources needed by the full application.

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Freiburger Str. 16

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