Periodic Reporting for period 1 - HIGH-MEMO (Ultra-High Speed memories for unprecedented cloud-computing performance)
Reporting period: 2022-04-01 to 2023-03-31
Static Random-Access Memories (SRAM) are bottlenecks. In IoT devices, they consume significant power when the device is idle. In high performance applications such as telecommunication infrastructure, data centres, and stationary devices they limit the processor performance. Xenergic’s mission is to design SRAM that revolutionise system-on-chip power efficiency. For IoT devices, we design SRAM that reduce energy consumption by 70-90% when the device is idle. For high performance applications our SRAM have the potential to reach 2-3x higher speed and to reduce energy consumption by 30% compared to competing SRAM. To capitalise on a >€280B annual market opportunity, we provide our customers with IP on SRAM design tailored to their requirements and profit from royalties on their sales. Our ultra-low energy memories are gaining strong traction from leading semiconductor companies. Now, with the investment from the EIC Accelerator, we aim to make our ultra-high-speed memories market-ready in an advanced FinFET Technology.
The main focus of the project activities is the development of Ultra-High-Speed (UHS) and High-Speed Turbo (HSTB) compilers and verifying them on silicon. After porting both architectures to the new technology all instances were analyzed in simulation and optimized for the PPA (power, performance, area) target. This step included technology and tool integration, checking documentation, characterizing critical memory elements and running iterative experiments to find the best configuration for device choice and dimensions, and finally verifying the designs across all relevant process corners and temperatures. The requirements for integration of assist and redundancy were also investigated and pushed to design. Following this work, the development of compiler leaf cells (building blocks) in layout has started. With the advancement of leaf cell design, higher complexity blocks have been assembled and verified up to the completion of first full memory instances for compiler validation. Post-layout simulations on these designs are being executed and further optimization loops for post-layout impact mitigation are ongoing.
In parallel to design and simulation process, the flow for generating models and the characterization flow for finfet technology has been further developed and integrated to our generic compiler flow.
The memory characterization flow is currently in place and the standard front-end memory models can be generated. These models have been verified and at this stage, we are able to provide all FE models which are required for a memory integration in a digital flow and silicon submission.
In parallel to design and simulation process, the flow for generating models and the characterization flow for finfet technology has been further developed and integrated to our generic compiler flow.
The memory characterization flow is currently in place and the standard front-end memory models can be generated. These models have been verified and at this stage, we are able to provide all FE models which are required for a memory integration in a digital flow and silicon submission.
The initial results are promising and we see a high potential in reaching the milestones of our target goal for UHS and HSTB. We still need to put more effort and further improve the design towards even better power-performance and area-cost balance. This is an ongoing activity and is an iterative process. The technology used in this work is quite heavy and complex and as expected, design loops take more time and higher resources compared to older technologies.