As a feasibility and application study, the HIPERLOGIC project will yield an innovative masterslice chip structure of high functional density. The objectives of high system performance at low power consumption will be achieved due to an innovative silicon-on-insulator CMOS process with three-dimensional integration and a circuit design optimally tuned to this technology. The CAD environment will integrate both an existing prototype technology-independent system level synthesis, and novel technology. In this project, all partners will bring together their expertise and knowledge in order to achieve the breakthrough in high performance, low power, application specific integrated circuits by the synergy of their joint activities.
The HIPERLOGIC project is aimed to push today's CMOS based integrated circuits into new regions of integration density, circuit performance and reduced power consumption. It will extend the limits of today's best performance/power ratios by a factor of 1000. Especially achieving low power consumption of CMOS circuits while maintaining speed is crucial for personal portable computing systems in consumer, industrial, and automotive applications.
In order to realize this rate of progress, synergy and harmonization of CMOS technology, circuit and system design are the essence of this project. The participating institutes have distributed strengths in all these areas in order to master the complex interactions of required technologies like silicon-on-insulator, three-dimensional integration, new circuit topologies, power-driven synthesis and compatible system design. While the overall result is aimed for an introduction in the year 2000, spin-offs will be available at many milestones for early industrial exploitation. Exemplary circuits and system demonstrators will be identified.
Funding SchemeCSC - Cost-sharing contracts