Skip to main content

Application specific processor and instruction set


The aim of the project is the development of a chip capable to undertake the execution of the baseband algorithms for families of cellular and cordless phones.

More in particular, the algorithms for a multi-mode terminal will be addressed, supporting the DECT and GSM/DCS1800 standards. The architecture will be either ASSP (Application Specific Standard Processor) or ASIP (Application Specific Instruction Set Processor). In this context the ASSP top-down approach within OMI will be explored by focusing on the SPARClet OMI-core with the appropriate co-processor and library extensions to be made. The expected capabilities of such IC should include microcontroller and DSP functionalities. The proposed ASSP approach would shrink the classical multi-chip implementation into a one chip solution. The ASIP path, on the other hand, comprises the design of a new application-specific DSP processor core that is tuned to the multi-mode terminal application, and that will be optimized for low power dissipation. This path includes a high-level validation step due to the use of a retargetable compiler. After benchmarking of the two alternative paths, one will be selected for eventual chip fabrication and validation.
Another objective is the incorporation of the chip into a full board (including RF stages) implementing a DECT terminal in order to be tested in a DECT environment. Moreover the chip will be validated in a GSM environment. A top down approach will be used for the design of an innovative product, using an established powerful OMI core and OMI methodologies. To serve the specific control and DSP functionality needs, the necessary coprocessing cells (memory mapped and/or instruction mapped) will be integrated on the same chip with the core processor. A nucleus of library objects will be developed aiming at their instantiation either on a SPARClet core based chip (ASSP, accepting custom adaptations) or on a semicustom programmable DSP (ASIP). The system state/flow diagram will be derived and with appropriate code profiling the necessary hardware extensions to the SPARClet core will be identified for the former case while in the latter case the full custom data path is conceived for customization. The baseband processing chip of the Multi-mode terminal is realized using either the inherent control functionality of the SPARC core and the building block extensions around it (organized either as instruction mapped or memory mapped coprocessing elements) or the retargetable compiler based custom ASIP path. All these elements are supported by an enhanced co-simulation/validation environment.
The result of the project shall be exploited in several ways:

- As a product offering of the Multi-mode terminal, through specific marketing actions (Multi-mode terminal complete solution, dual DECT and DCS-1800 system attached to GSM unit, standard component).
- As proprietary architectures supporting specific algorithmic families, licensing them to third parties and having as a reference the performances achieved by the participating system companies.
- As the specific "products" manufactured for benchmarking.
- As a viable generalized methodology and CAD tools for DSP design aiming at supporting both, custom signal processor design and co-simulation of hardware/software systems.

Funding Scheme

CSC - Cost-sharing contracts


Intracom Sa, Hellenic Telecommunications and Electronics Industry
19.5 Km Markopoulou Avenue 68
19002 Peania - Attika

Participants (5)

C. S.E.L.T. Centro Studi E Laboratori Telecomunicazioni S.P.A.
Via G. Reiss Romoli 274
10148 Torino
Abdijstraat 34
3001 Leuven
Inter University Microelectronics Center
Kapeldreef 75
3030 Heverlee
Italtel S.P.A. - A Stet and Siemens Company
Piazzale Zavattari 12
20100 Milano
Matra Mhs
La Chantrerie / Route De Gachet
44087 Nantes