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Non-volatile erase-write multi-level silicon integrated circuits

Objective

This project intends to provide an essential contribution with exploratory research on multi-level storage for NV memory applications. It consists of two phases:

- The first (12 months) is carried out by three Research Institutes (Universities of Bologna and Pavia in Italy and IMEC in Belgium). Industry, however, will contribute by:
-defining essential specifications;
-closely following the work;
-providing support for test chip realisation.

If the first Phase reaches satisfactory results, industry would participate directly in the second Phase Project with a leading role.

The first Phase consists essentially of a feasibility study, focused on the most critical issues for the realisation of multi-level NV products and will be split in two parts (6 months each):

- study and development of suitable programming and sensing schemes to be implemented on test chips; - experimental characterisation of such test chips.

- The second Phase, carried out by a larger consortium that would include a leading company in the field of NV memories, would last 3 years and be explicitly dedicated to the realisation of competitive NV memories based on the results of the first Phase.

The most important type of NV components are FLASH memories. From the point of view of multi-level storage, a major problem is that of correctly sensing closely spaced stored charge levels (also affected by imperfect charge retention). This problem is common to all types of NV memories, hence can be studied by means of EPROM cells, simpler to fabricate and providing worst-case conditions for cell sensing because of their limited threshold window.

The other major problem concerns cell programming (or writing), required to achieve tight distributions of multiple transistor thresholds. FLASH cell programming can exploit either hot electrons or Fowler-Nordheim tunnelling, and both these possibilities must be carefully investigated. In these cases too, it is convenient to use simpler test vehicles, such as HIMOS and EEPROM cells for hot-electron and tunnelling programming. The use of simpler devices to study the problems of FLASH memories will also allow to study directly the multi-level operation of other NV devices (EPROM, EEPROM and HIMOS) of significant market potential.

This project investigates the main problems associated with multi-level charge storage on floating-gate MOS transistors used to realise non-volatile (NV) memory cells capable to memorise more than one bit. Multi-level storage is of crucial importance for NV memories because it can multiply their capacity for a given technology, thus significantly reducing the "cost per stored bit".

Funding Scheme

ACM - Preparatory, accompanying and support measures

Coordinator

D.E.I.S. Universita diBologna
Address
Viale Risorgimento 2
40136 Bologna
Italy