Skip to main content

Embedded fault tolerant supercomputing

Objective

The major objective of the project is to provide a framework for the implementation of fault tolerance in embedded supercomputing applications. This framework will provide a flexible, standard approach for programmers making embedded supercomputing applications more dependable. This approach will shorten the time to market, facilitate software development, maintenance and upgrading, and reduce dependence on specific hardware.

Fault-tolerant functions will be accessible to application developers through the high-level API of the fault-tolerance library which extends Embedded PARIX (EPX). This will hide hardware-dependent features from the application programmer, guaranteeing that the application can be ported to standard hardware platforms and run-time kernels.

The target architecture of the project is an MIMD, homogeneous, distributed-memory, message-passing, multi-processor system. Work will be performed on a Parsytec embedded system, based on the PowerPC microprocessor. The operating system will be EPX and the programming language will be ANSI C / C++.

Important industrial end-user applications of embedded parallel computing will drive the requirements and demonstrate the results. The applications include mail sorting (AEG) and control of high-voltage substations (ENEL).

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

PARSYTEC COMPUTER
Address
Auf Der Huels 183
52086 Aachen
Germany

Participants (4)

Aeg Electrocom Gmbh
Germany
Address
Bücklestrasse 1-5
78459 Konstanz
ENEL SPA
Italy
Address
Viale Regina Margherita, 137
00198 Roma
Siemens Electrocom Gmbh
Germany
Address
Bücklestrasse 1-5
78467 Konstanz
TXT E-SOLUTIONS SPA
Italy
Address
Via Frigia 27
Milano