The goal of this project was to develop a design technology environment for the interactive synthesis of complex integrated systems as required for the realisation of real-time information processing subsystems, such as image and graphics processing, post-ISDN home and business peripherals, HDTV, radar, coprocessors, data compression, etc. This would allow system designers to explore different implementation alternatives in terms of several cost criteria (such as chip area, throughput and power dissipation) in a more efficient way. At the same time, the total design time and design effort would be reduced by an order of magnitude.
The goal of interactive silicon compilation for high performance integrated systems (SPRITE) is to develop a computer aided design (CAD) system for the interactive synthesis of the complex systems required in applications such as image processing, graphics processing, radar, digital television, office automation, mobile radio, etc.
The goal of this project is to develop a computer aided design (CAD) environment for the interactive synthesis of complex integrated systems as required for the realization of real time information processing subsystems.
The initial part of the project involved the definition of the architectural styles and the definition of a new language/data structure, the sprite input language (SIL). SIL was released into the public domain to facilitate the setting of standards in the field of high level synthesis. In addition, the consortium has been involved in the SILAGE/DFL standardization committees that have standardized SILAGE/DFL as a system specification language for digital signal processing (DSP) systems. 3 prototype compilers have been developed that will be released for evaluation in key application areas. A full suite of high level compilers and a set of synthesis environments, such as CATHEDRAL, PHIDEO and CHESS, will be targeting several market niches.
Other technologies developed within the project, such as the datapath compiler CHOPIN and the timing analysis system SLOCOP, have proven useful in current industrial application specific integrated circuit (ASIC) development. In addition CHOPIN received the Flanders Technology Award for achievement in 1991.
The project also defined and implemented a synthesis tools framework and common data structure which allows the transfer of tools between the participants. Other tools to assist in the transfer of technology between partners have also been implemented: a layout procedural interface (LPI), and a high speed data interchange mechanism (SPOOK) that allow real time program to program communications via procedural interfaces.
The behavioural system specifications were described in a mixed functional/procedural language (e.g. VHDL, SILAGE). The synthesis system compiles the specifications in a chip layout using a mixture of knowledge-based and algorithmic techniques. It is oriented towards a set of generic high throughput target architectures with a variable degree of microcode programmability and parallelism. The underlying formalised knowledge base is extracted from the design of industrial demonstrator chips.
Interactivity was based on a pragma concept. Without changing the behavioural specification at the top level, the designer can give structural "hints" to the compilers at different hierarchical design levels. This allows the designer to explore trade-offs in terms of quality factors, such as power and area, for a required throughput as a function of the architectural choice. It also determines hardware, firmware and software trade-offs. In addition, CAD software for both on- and off-chip interprocessor communication was developed.
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