Skip to main content

Focus driven hierarchical simulation technology for reactive embedded systems

Objective



This project is a reaction to shortcomings in the validation and verification techniques of hardware/software co-design systems. State-of-the-art for checking and verifying correctness in a hardware/software co-design system is using simulation techniques and for some special request in the design the application of formal verification techniques.

The shortcoming of simulation techniques is nowadays often the low speed of the simulation software since it has to handle very large designs with often too detailed design information. In some cases simulation techniques applied to a VHDL design are not feasible any more since too much time is consumed until getting a result. Beside that, memory requirement problems might cause that simulation is not possible at all.

The solution this project intends to provide w.r.t. this shortcoming is automatic or semi-automatic abstraction of information in order to speed up the simulation. Dependent on the information requested the abstraction might have a different focus such that the requested information is not lost during the abstraction. Pre-results show that such an abstraction either to VHDL or C/C++ can speed up the simulation significantly. In addition to that parallel simulation for different parts of a design might be a solution to the problem.

Since several steps in the abstraction process may be performed in a hand-tailored manner the correctness of the abstraction is in general not guaranteed. In order to check the correctness of the abstraction process formal verification techniques are used. After the model has undergone the abstraction it is provided to the formal verification software as an input in order to speed up the verification. To cope with large designs the verification software will be based on test generation techniques.

Formal verification techniques in general are less suitable with rising circuit complexity. Especially when dealing with bus protocols existing techniques are no more applicable. The formal verification techniques developed for the verification of the abstraction process will be applied to several bus protocols provided by the industrial partner in order to get a feeling for the potential and the limits of bus protocol verification.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

Fraunhofer Gesellschaft
Address
Schloss Birlinghoven
53754 Munich
Germany

Participants (3)

POLITECNICO DI TORINO
Italy
Address
Corso Duca Degli Abruzzi 24
Torino
Siemens Nixdorf Informationssysteme Ag
Germany
Address
Otto-hahn-ring 6
81739 Munchen
Technische Universität Wien, Institut Für Technische Informatik
Austria
Address
Treitlstrasse 3/E182
1040 Vienna