Final Report Summary - OSIRIS (Open silicon based research platform for emerging devices)
During the period of the OSIRIS project, we have successfully established the Open Silicon based Research platform for emerging devices, which provides valuable solutions for many emerging devices that can be fabricated through the platform based on silicon technology, but may not use silicon as the active semiconductor material any longer. The established platform strengthens our capability to conduct world-class research on future nano-electronic technology nodes according to ITRS roadmap specifications beyond 2015.
This project covers a broad range of critical research issues that can be foreseen as groundbreaking topics for the period beyond 2015. Five relevant research fields have been explored and substantially advanced: (1) Fully depleted CMOS technology for Access to European Universities. Fully depleted CMOS technology has been developed to serve as a platform to integrate a variety of advanced CMOS techniques with new materials and functionalities. With a self-aligned double patterning sidewall transfer lithography technique, the critical dimension can be reduced down to 15 nm for on-chip fabrication of silicon nanowires. With the dopant segregation technique, Schottky barrier MOSFETs can be fabricated with effective barrier height less than 0.15 eV, which is a must for these devices to outperform doped source/drain MOSFETs. With the Atomic Layer Deposition (ALD) technique, novel and unique TmSiO/HfO2/TiN gate stacks are fabricated to exhibit extremely low equivalent oxide thickness of 0.6 nm. With the room-temperature direct wafer bonding technique, strained and unstrained Germanium on insulator (GeOI) substrates can be fabricated. In addition, epitaxially grown in-situ doped SiGe has been implemented as source/drain modules in various transistor devices. Through the collaboration with other EU projects, the platform has been known and accessible to many European universities, which greatly strengthens and extends our collaboration with European academia. (2) Low frequency noise in advanced silicon nano electronic structures. In-depth study of noise performance has been conducted to thoroughly evaluate the advanced devices fabricated in OSIRIS. It has been confirmed that low Schottky barrier devices exhibit excellent noise performance, and the dual-layer dielectric (Tm2O3/TmSiO) shows better noise performance even than the SiOx/HfO2 stacks. (3) Silicon nanowire based biosensor. High-density arrays of silicon nanowires have been fabricated in OSIRIS for highly sensitive and selective sensors to realize label free detection of DNA and protein biomolecules in low concentration. Each sensor array consists of 32 × 32 pixel matrix (each pixel comprises a SiNW with dimension of 60 nm × 20 nm) and 8 input-output (I/O) pins. The 1024 individual SiNWs can be read-out sequentially and employed for real-time charge based detection of molecules in liquids or gases. (4) Silicon-based optoelectronic devices. So far photonic structures are usually fabricated by the low-throughput electron-beam lithography and on the expensive SOI wafers. In OSIRIS, by incorporating high-k ALD double slot waveguides with selectively grown Ge PIN photodetectors, photonic chips have been successfully fabricated on bulk silicon wafers through our cost-effective CMOS platform. Furthermore, in a recent photonic chip, the novel graphene photodetectors have also been successfully embedded into the waveguide slot layer. (5) Graphene-based devices and techniques. Graphene-based FETs (GFETs) have been considered promising devices to be co-integrated with silicon technology because of the excellent electronic properties of graphene. With a systematic model-based comparison of radio frequency performance metrics, we assess that future GFETs have great potential to match and exceed CMOS, potentially up to THz operation. We also fabricated novel graphene-based devices and investigated their integration with CMOS technology, including vertical graphene base transistors, piezoresitive graphene pressure sensors, and graphene-based photodetectors. In addition, as a novel deposition technique, inkjet printing has been developed to directly write massive uniform patterns of graphene and other 2D materials. Transparent conductors, thin film transistors, supercapacitors, and photodetectors have all been printed. The technique has shown promise for emerging printed electronics and has potential to be integrated into the CMOS platform.
The OSIRIS project has fundamentally enhanced our research group and collaboration with other European research groups, and has enabled us to participate in a very strong way within the European projects, such as NANOSIL, NANOFUNCTION and the pilot flagship FET open Guardian Angel. Benefiting from the outputs of OSIRIS, we successfully acquire considerable funding from other international and national agencies. As an important follow-up and still supported by ERC, we will conduct a Proof of Concept project, iPUBLIC -- Inkjet Printed Ultrafast Batteries and Large Integrated Capacitors, to explore preliminary commercialization processes for innovative ideas generated on the basis of the outputs of OSIRIS.
This project covers a broad range of critical research issues that can be foreseen as groundbreaking topics for the period beyond 2015. Five relevant research fields have been explored and substantially advanced: (1) Fully depleted CMOS technology for Access to European Universities. Fully depleted CMOS technology has been developed to serve as a platform to integrate a variety of advanced CMOS techniques with new materials and functionalities. With a self-aligned double patterning sidewall transfer lithography technique, the critical dimension can be reduced down to 15 nm for on-chip fabrication of silicon nanowires. With the dopant segregation technique, Schottky barrier MOSFETs can be fabricated with effective barrier height less than 0.15 eV, which is a must for these devices to outperform doped source/drain MOSFETs. With the Atomic Layer Deposition (ALD) technique, novel and unique TmSiO/HfO2/TiN gate stacks are fabricated to exhibit extremely low equivalent oxide thickness of 0.6 nm. With the room-temperature direct wafer bonding technique, strained and unstrained Germanium on insulator (GeOI) substrates can be fabricated. In addition, epitaxially grown in-situ doped SiGe has been implemented as source/drain modules in various transistor devices. Through the collaboration with other EU projects, the platform has been known and accessible to many European universities, which greatly strengthens and extends our collaboration with European academia. (2) Low frequency noise in advanced silicon nano electronic structures. In-depth study of noise performance has been conducted to thoroughly evaluate the advanced devices fabricated in OSIRIS. It has been confirmed that low Schottky barrier devices exhibit excellent noise performance, and the dual-layer dielectric (Tm2O3/TmSiO) shows better noise performance even than the SiOx/HfO2 stacks. (3) Silicon nanowire based biosensor. High-density arrays of silicon nanowires have been fabricated in OSIRIS for highly sensitive and selective sensors to realize label free detection of DNA and protein biomolecules in low concentration. Each sensor array consists of 32 × 32 pixel matrix (each pixel comprises a SiNW with dimension of 60 nm × 20 nm) and 8 input-output (I/O) pins. The 1024 individual SiNWs can be read-out sequentially and employed for real-time charge based detection of molecules in liquids or gases. (4) Silicon-based optoelectronic devices. So far photonic structures are usually fabricated by the low-throughput electron-beam lithography and on the expensive SOI wafers. In OSIRIS, by incorporating high-k ALD double slot waveguides with selectively grown Ge PIN photodetectors, photonic chips have been successfully fabricated on bulk silicon wafers through our cost-effective CMOS platform. Furthermore, in a recent photonic chip, the novel graphene photodetectors have also been successfully embedded into the waveguide slot layer. (5) Graphene-based devices and techniques. Graphene-based FETs (GFETs) have been considered promising devices to be co-integrated with silicon technology because of the excellent electronic properties of graphene. With a systematic model-based comparison of radio frequency performance metrics, we assess that future GFETs have great potential to match and exceed CMOS, potentially up to THz operation. We also fabricated novel graphene-based devices and investigated their integration with CMOS technology, including vertical graphene base transistors, piezoresitive graphene pressure sensors, and graphene-based photodetectors. In addition, as a novel deposition technique, inkjet printing has been developed to directly write massive uniform patterns of graphene and other 2D materials. Transparent conductors, thin film transistors, supercapacitors, and photodetectors have all been printed. The technique has shown promise for emerging printed electronics and has potential to be integrated into the CMOS platform.
The OSIRIS project has fundamentally enhanced our research group and collaboration with other European research groups, and has enabled us to participate in a very strong way within the European projects, such as NANOSIL, NANOFUNCTION and the pilot flagship FET open Guardian Angel. Benefiting from the outputs of OSIRIS, we successfully acquire considerable funding from other international and national agencies. As an important follow-up and still supported by ERC, we will conduct a Proof of Concept project, iPUBLIC -- Inkjet Printed Ultrafast Batteries and Large Integrated Capacitors, to explore preliminary commercialization processes for innovative ideas generated on the basis of the outputs of OSIRIS.