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Thermal management with carbon nanotube architectures

Final Report Summary - THEMA-CNT (Thermal management with carbon nanotube architectures)

Executive Summary:

Executive summary

To overcome the difficulties in the contemporary thermal management of Si components and packages made of ceramics and organic laminates, in this project we proposed novel and scalable cooling technologies that utilize carbon nanotubes and their architectures integrated on various electrical components to achieve high cooling efficiency on large area Si chips, on ceramics/polymer packages and on micro hot spots.

Our efforts in the project were focused on generating specifically tailored nanostructured carbon based materials that are crucial for the successful development of new thermal management technologies in current and future electronics. The technologies we developed will enable direct integration of carbon nanotube architectures in electrical components and make a feasible protocol for upscaling for industrial use. As carbon nanotubes are post-mounted (and in some cases directly grown) on Si chips/wafers and ceramic packages the process is compatible with conventional Si fabrication and micromodule packaging technologies, i.e. the technology provides a ready protocol for large scale production of such components.

Because of the compatibility with current technologies, the nanotube based cooling devices and production technologies are cost effective and have great commercial value. Since thermal management is one of the most crucial issues in today’s high performance electrical devices (processors, power transistors), the market potential of our innovation is enormous, potentially exceeding several billion total sales every year.

The project was coordinated by the University of Oulu, Finland and had another six partners from Sweden (Chalmers Tekniska Hoegskola AB, SHT Smart High-Tech AB), from Belgium (Interuniversitair Micro-Electronica Centrum VZW, ON Semiconductor Belgium BVBAH), from Spain (Universidad Del Pais Vasco) and from Hungary (University of Szeged).

The scientific outcome of the project was excellent, mainly thanks to the theoretical work of Universidad Del Pais Vasco. They have produced over 50 papers, talks and lectures related to the project. The project had over 100 scientific appearances in the three years. Other groups were focused on the experimental and, with the leadership of University of Szeged, the health and safety matters related to carbon nanotube production and the final coolers. ON Semiconductor Belgium is the primary end user of the developed technology and will most likely proceed with patenting and production, thus strengthening the European economy.

Project Context and Objectives:

A summary description of project context and objectives

Modern applications require more and more functionalities (e.g. safety systems in modern cars or faster CPUs in computers), resulting in a higher energy demand.

The continuously increasing packing density of transistors and the corresponding problem of heat dissipation is a major problem in high performance IC technology. In classical cooling setups, heat-sinks/coolers are integrated on the hot surface, or tiny flow channels are formed in the bulk of the component. In both cases the component/cooler geometry, thermal conductivity and the film coefficients at the interfaces of solid and coolant gas/liquid media play a crucial role and need to be optimized for every particular case. The International Technology Roadmap for Semiconductors (ITRS) provides both short term and long term power dissipation predictions for high-performance computers. According to these predictions, the power dissipated at the chip level will increase far beyond 100 W/cm2 from the current value of ~60 W/cm2 within the next few years. This trend is raising a claim to develop novel cooling methods and/or utilize new materials by which heat can be dissipated in a more efficient manner.

Improving the cooling performance of traditional conductive/convective cooler devices could be accomplished by replacing the large finned copper and aluminium blocks with other materials of better thermal conductivity (κAl ~ 370 W•m-1•K-1, κCu ~ 400 W•m-1•K-1).

Ultra-high-density 3D packaging is a novel technology for everyday’s computing. Three-dimensional chip stacking with vertical interconnections through Si chips is potentially the best technique of semiconductor system integration. The technology is attracting interest due to its high density capability, and it is expected to ultimately become a way of integrating various devices. One of the latest market researches (Yole development, Hwww.yole.frH) show that 3D wafers – with through silicon via (TSV) in this case - will be shipped in millions and have the potential to impact as much as 25% of the memory business by 2015. Excluding the memories, the analysis show that 3D wafers could account for more than 6% of the total semiconductor industry by 2015.

The thermal management of the 3D chip stacking structure is an essential issue. There are various case studies in the literature on factors that affect heat dissipation, such as inter-chip encapsulant, dielectric layer and thermal vias, based on common materials, such as copper. Yole development’s latest analysis shows that the equipment market for 3D-TSV manufacturing tools will rapidly expand above 1B$ by 2013. 3D-TSV Equipment forecasts have been realized over the 2006-2015 time period both in units and in M$. They include shipments and sales forecasts for wafer bonders / chip bonders / etching-drilling / plating / lithography / deposition-coating / temporary bonding / grinding-thinning / inspection & metrology / test tools. Meanwhile, the 3D-TSV market for advanced materials is forecasted to break the 1B$ volume by 2015. The analysis include sales in volume and in M$ for advanced photo-resists / adhesives / gas / advanced substrates and specific chemistries.

Apart from a higher density of active devices (and thus higher power density), as in the 3D stacking described above, there is also a trend going to higher total power dissipation in devices. Applications as diversified as hybrid cars, PV inverters, lighting, (wind) energy, the demand for power devices is increasing steadily. Power electronics is and will remain one of the most attractive branches of the semiconductor industry over the next decade. In 2012, the market for semiconductor devices (discrete, modules and ICs) dedicated to the power electronics industry reached $20 billion.

These devices with very high power densities only function with an excellent thermal management system. The superior thermal conductivity of individual carbon nanotubes (κCNT ~6000 W•m-1•K-1) has prompted suggestions of their applications in thermal management of these electronic systems. With the quick development of synthesis methods, various types and forms of CNTs became available and affordable nowadays; therefore it is a natural step to test how feasible they are in 3D and traditional IC thermal management applications.

Carbon nanotubes can be applied in many different ways to manage the thermal budget of an electrical component/device. The research groups participating in this project have performed pioneer work in this field when demonstrated chip cooling with integrated carbon nanotube films and structures. Using and eventually further developing the earlier approaches we proposed, thermal management of high power electrical chips and packages using on-component films, microstructured finned coolers, thermal adhesives and thermal vias, are all based on tailored carbon nanotube architectures. Emphasis was placed on compatibility of CNT technology with conventional back-end processing in Si chip fabrication and Si packing technology, based on thick film ceramic or organic laminate/moulding technologies, to enable ready upscaling and cost effective production of devices based on the novel carbon nanotube based technologies.

To overcome the difficulties in the contemporary thermal management of Si components and packages made of ceramics and organic laminates, in this project we proposed to develop novel and scalable cooling technologies that utilize carbon nanotubes and their architectures integrated on various electrical components.

The ultimate objective of the project was to implement carbon nanotube architectures in Si chip and ceramic/organic package platforms to remove excess heat from the components. The program has executed extensive research on:

- Carbon nanotube synthesis being compatible with standard Si fabrication and ceramic/organic laminate technologies using catalytic chemical vapour deposition and plasma-enhanced chemical vapour deposition methods.
- Direct synthesis of carbon nanotubes on Si chips and on ceramic/organic packages to form on-component heat sinks and thermal vias using technologies that are directly applicable for large scale production.
- Applicability of carbon nanotube based isotropic and anisotropic thermal interface materials transferred to electrical components by imprinting and soldering methods.
- Experimental determination of thermal resistivities of interfaces that carbon nanotubes and adhesives based upon those form with other materials such as Si, SiO2, ceramics, polymers and metals.
- Multi-scale computational study of heat transport in terms of (a) phonon transport through interfaces using molecular dynamics simulations and (b) macroscopic heat transport using continuum models with the finite element method.
- The potential pollution of laboratories and our environment due to production of nanotubes and use of devices with integrated carbon nanotube structures.

As shown by the above list, our efforts in the project were focused on generating specifically tailored nanostructured carbon based materials that are crucial for the successful development of new thermal management technologies in current and future electronics. The technologies developed will enable direct integration of carbon nanotube architectures in electrical components and make a feasible protocol for upscaling for industrial use. As carbon nanotubes were directly grown and also post-mounted on Si chips/wafers and ceramic packages, thus the process is directly compatible with conventional Si fabrication and micromodule packaging technologies, i.e. the technology provides a ready protocol for large scale production of such components. Because of the compatibility with current technologies, the nanotube based cooling devices and production technologies will be cost effective and easy to commercialize. Since thermal management is on of the crucial issues in today’s high performance electrical devices (processors, power transistors) the market potential of our innovation is enormous, possibly exceeding several billion € total sales every year.

Project Results:

A description of the main S&T results/foregrounds

The project had the following work package layout for the 36 months:

WP 1 Benchmarking
WP 2 Test chips and package fabrication
WP 3 Optimized synthesis of CNTs
WP 4 Direct CNT growth on chips and packages
WP 5 Post-mounted CNT coolers on chips and packages
WP 6 Thermal measurements
WP 7 Multi-scale modeling
WP 8 Implementation of CNTs onto CMOS technology - demonstration of large scale processing
WP 9 Component reliability
WP 10 Environment issues
WP 11 Exploitation and dissemination
WP 12 Project management

In the following we describe the original objectives and the main S&T results/foregrounds for work packages 1-11. WP 12 was dedicated to project management issues.

WP 1 Benchmarking


In this work package a benchmarking was made of thermal budgets for silicon chips and their packaging. Current solutions for thermal power dissipation on chip and in the package were investigated. A roadmap was established for future evolutions concerning thermal dissipation, based on existing roadmaps in it served us as a guideline for the projects’ developments. From the roadmap information, the boundary conditions and specifications for the CNT technology were be determined.

The following concept was established:

Thermal management issues continue to be a hot topic in the semiconductor industry. In fact, as new devices are developed that require faster circuits in smaller areas, the issues are becoming more and more critical. This project aims at the complete electro-thermal simulation of smart power applications and is therefore particularly important for automotive semiconductor solutions.

Thermal management and accurate simulation and prediction of thermal hot spot and subsequent current distribution are very important in today’s ICs. In smart power applications, switching large currents (~1-10 A) over moderate voltages (~20-80V) the challenge is threefold:

• The decrease of the driver area due to device optimisation (e.g. novel device concepts, shrinking in technology dimensions) leads to a higher power density in silicon. As a result, the temperature will rise substantially, and will lead to a non-uniform current distribution in the driver. If the driver is not properly designed (current crowding) or of proper dimensions (too small), the temperature can reach the critical temperature and result in electro-thermal destruction of the driver.
• The trend for more integration of e.g. high density CMOS, embedded memory, power drivers etc. on the same chip requires a very accurate prediction of the temperature rise across the die in order to guarantee the proper operation of e.g. the memory, the micro-controllers, etc. Moreover, a precise knowledge of the temperature rise is necessary to assess and ensure the reliability of automotive power ICs.
• Due to the high level of system integration (e.g. sensors and controlling logic), the chip will be located close to heat sources. Examples for automotive applications are: close to the breaks, to the engine compartment, into the oil breaking system. These high temperature applications require an accurate cooling solution of the temperature of the total system.


On chip level and during chip design, a lot of attention is paid to thermal management of the device. Related to the application the best possible solution for packaging is proposed. However, all new developments for an improved heat transfer out of the silicon, will further enhance the performance, the reliability (and the safety) of future power electronics.

Improved Thermal management will allow better controlled High Temperature:

• Smaller area: Dissipate more on-chip → use small sized drivers → gain area → lower cost
• New applications: Moving the ASIC into eg. oil to measure the oil temperature → Shortens cables, Remove connectors → is cheaper
• Less space:
• Combine distributed ASICs into 1 ASIC
• Reduce required size by integrating the ASIC into the (hot) module.

Project technology roadmap

A strong statement to support our project technology roadmap can again be found in the ITRS Roadmap on System in Package (SiP): “The main bottlenecks in reducing the junction-to-ambient thermal resistance are the thermal resistances of the thermal interface material (TIM) and the heat sink. The need for TIMs that exhibit mechanical stability during chip operation, adhesion, and conform to fill the gaps between two rough surfaces generally yields materials with relatively low thermal conductivity, and thus correspondingly high thermal resistance. To address this need, new TIMs are being explored. In one example, the integration of carbon nanotubes (CNTs), which exhibit very high thermal conductivity, within a TIM’s matrix is being investigated. Further in depth information may be found in the 2007 ITRS Chapter on Emerging Research Materials. For example, it has been shown that the overall thermal conductivity of epoxy can increase substantially with the integration of CNTs. However, their integration with such materials requires carefully processing to prevent poor dispersion and weak bonding with the polymer/epoxy matrix in order for the overall thermal conductivity to substantially increase. Research is ongoing to fully demonstrate CNTs as TIMs.”

WP 2 Test chips and package fabrication


In WP 2, the concepts discussed in WP 1 were implemented in test vehicles. A suitable test chip was selected with test structures that allowed verifying the technology solutions proposed in WP 1. In the same way, innovative package constructions incorporating carbon nanotubes were set to be developed. Test chips and test packages were only to be used to verify the new concepts in an experimental way. Thermal models of the test chips and the packages were to be constructed, and checked through experimental verification. The models were used further as input for the CNT modeling.

Test chip and thermal package design and Si technology modification

In the reports an overview was given on the test chips and test packages which were to be used in the Thema-CNT project. The test chips were to be used for growing Carbon Nanotube structures as well as for attaching pre-grown structures. For the test packages, a standard power package was analyzed and possible areas where CNT as heat conducting materials can be used were analyzed. Finally, possible or necessary ways of changing the silicon production technology in order to grow CNT on it was examined.

Test chips

Silicon chips which are used in the electronics industry can be divided into 2 major categories: discrete devices and integrated circuits. Discrete components are elementary electronic devices, like transistors or diodes, constructed as a single unit. These devices generally consume a lot of current resulting in the creation of a lot of heat. The physical dimensions of high-current discrete components are mostly large compared to the total size of the silicon it is processed on, and therefore heat up the total silicon area resulting in a large hot area.

On the other hand there is the Integrated Circuit (IC), which is a combination of several discrete devices onto a silicon substrate. The currents used in integrated circuits are lower than in discrete devices, but because of the large number of these devices used in one circuit also a lot of heat can be created. However the main problem of ICs is the creation of hot spots: because of the small size of the devices on the large silicon chip, they will heat up the silicon very locally. Because these hotspots are located on the active side of the chip (topside), this makes it hard to dissipate this heat because on that side there is only the thermal insulation mold material of the package. Therefore also the temperature of these hotspots can get higher than that of large areas, as shown in Figure 1. In the case of a static 2.5W heat source, the maximum temperature of the uniform source is 60°C whereas for a hotspot of the same power, the maximum temperature gets up to over 280°C, which can damage the silicon chip.

Figure 1. 2.5W Static heat source applied uniformly over the chip (left) or as a hotspot (right)

Inside the Thema-CNT project, both types of chips meant to be used to test, as both uniform and hot spot heating create problems.

First prototypes of the test chips and packages for direct growth of carbon nanotubes and also for post-mounting of these nanotubes on the silicon realized by month 12 at IMEC/ON Semi team in parallel with UOulu efforts.

Figure 2. Schematic picture of the structure of test chip 1.0; a) Cross-section of the chip; b) Shapes and dimensions of the conductors with hot spots. For every hot spot sample with MWCNT layer there was reference sample without the MWCNT film; c) schematic picture of different composition of the MWCNT films, which are grown as an array, as dots and as solid area.

From IMEC/ON Semi, a total of 3 different kinds of test chips are adopted. The first ones are very basic chips without any patterning. On the second kind of chips already a pattern is included, and this in both the isolation as the metal layer. The third kind of chip is complete functional test chips with for instance heaters and temperature sensors. With these chips, it is possible to measure the performance of the carbon nanotube cooling structures.

Figure 3. Schematic picture of Oulu’s test chip for large area cooling

Do to the foreseen delays in fabricating the advanced functional chips at ON Semi, UOulu team has started a functional but more simplified test chip development at month 12. These chips are to provide test platforms for testing on chip grown and post mounted carbon nanotube coolers for large area and also for hot spot cooling.

Figure 4. Schematic picture of test chip for hot spot cooling

Picture 4. Laser scribed alumina samples on 2 inch alumina sheet from both sides.

At the time of midterm report UOulu had 6 generation of functional chips developed and tested. The test results are reported WP4.

Second generation chip-sets and ceramic packages improved for CNT integration considering the experience gained in WP3 on the first prototypes

New family of test chips were developed and measured, manly at the more flexible Oulu test chips.

Second generation prototypes of the test chips and packages for direct growth of carbon nanotubes and also for post-mounting of these nanotubes were established. In total 4 different kinds of test chips are defined

The cooling performance of CNT films (heat sinks) was measured with thermal imaging infrared camera. The thermal images were taken from the shortest possible focusing distance.

Picture 5. Measurement performed with hot spot heater having 3x3 array of CNT pillars on top. On left without forced cooling air gas flow and on right with cooling air gas flow of 10 l/min is shown.

The cooling performance measured on the first generation of chips was limited and several manufacturing issues were there.

WP 3 Optimized synthesis of CNTs


WP3 was led by the UOulu team, focusing on the optimization of CNT synthesis (PECVD and CCVD) on materials that are used in Si fabrication and in packaging. The goals were (a) to provide high quality aligned CNT films grown by CCVD for post-mounting applications and (b) to optimize PECVD growth of CNTs on thermally sensitive electrical components, and (c) most importantly to ensure that both approaches are compatible with the conventional fabrication methods in Si processing and packaging. This optimization step was vital for realistic upscaling of the CNT integration into real components in later work packages (WP4, WP5 and WP8).

Early in the project we demonstrated the growth of freestanding and supported films (on SiO2 and Al2O3) of highly aligned MWCNTs with high graphitic content

Tailored synthesis of highly aligned nanotube films for post-mounting and thermal interface applications applied in subsequent work packages (WP5 and WP8) were carried out. The synthesis was performed by catalytic chemical vapour deposition (CCVD) of CNTs from metallocene/xylene precursors at temperature 770 °C on SiO2.

Large area growth was successfully carried out. The maximum possible footprint was around 23x23mm2. The maximum achievable lengths of the films were about 3mm. After a modified CCVD reactor design the system yield slightly shorter tubes, when comparing the maximum lengths achieved with the same growth time. However the obtained tubes are better quality and maybe more importantly the system performed better in overall, requiring less maintenance.

Micropatterned films of MWCNTs grown by PECVD on Si or SiO2 test substrates at low temperatures.

With thermal CVD several experiments have been made with different catalyst, precursor and temperature combinations in order to achieve low temperature (< 500 oC) CNT growth. Catalysts have included PVD deposited Fe and Ni and drop casted Co, Fe and Ni (on Al2O3) nanoparticles. As precursor xylene, methanol, cyclopentenes, cyclohexene, and THF have been tested.

The best results have been achieved with Ni and Co as catalyst (Ni as sputtered and as nanoparticles, Co as nanoparticles) and oxygen containing precursor methanol and cyclopentene oxide.

The lowest temperature in which MWCNTs have been grown is 470 oC with Co as catalyst and cyclopentene oxide as precursor.

With Chalmers PECVD equipment nice, high-quality MWCNTs can be grown at high temperatures (~700 oC). These MWCNT structures can be transferred onto chips and post-mounted.

Figure 6. Aixtron Black Magic 2-inch PECVD system at the University of Oulu

With Oulu’s PEVCD system, the lowest temperature in which CNT/CNF material have been produced was ~500 oC. This system was partially funded by the Thema-CNT project.

Micropatterned films of MWCNTs and CNFs on grown by PECVD on 2 inch size wafers at temperatures below 400°C.

Originally the goal was to achieve low temperature CNT growth on 4 inch wafer but it has turned out that 4 inch CNT growth system is simply too expensive in the scope of this project. Also the goal of CNT growth below 400 °C was very ambitious, it has turned out that growing CNTs with adequate quality in low temperature is very challenging.

As a compromise large area CNT growth was demonstrated on 2 inch wafer with high temperature growth. This demonstrates that high temperature process is up-scalable and these achievements can be utilized in post-mounting. Demonstration included CNT films with different thicknesses grown on micropatterned wafer done by optical photolithography.

Figure 7. Cut 2 inch wafer with micropatterned CNT layer

Selective CNT growth on 2 inch wafers with controlled CNT film thicknesses was successful. Further optimization on the process made possible to achieve over 1mm thick CNT layers on 2 inch wafers.

Figure 8. CNT film thickness vs. growth time with linear fit

WP 4 Direct CNT growth on chips and packages


WP 4 followed the CNT growth technology studied and developed in WP3 but on real electrical components provided by WP2. Large area cooling and microscopic hot spot removal with carbon nanotubes grown by catalytic chemical vapour deposition (CCVD) and also by plasma enhanced chemical vapour deposition (PECVD) techniques on real Si chips and ceramic packages were carried out. In WP4 we developed novel technology protocols for carbon nanotube integration that are scaleable and compatible with the currently used Si chip fabrication and ceramic packaging techniques.

This work package had two tasks, task Direct CNT/CNF growth on real Si devices by PECVD and task Direct CNT growth on real ceramic components by CCVD. Both cases the task included an optimization step where the fin length and array density is adjusted with computational fluid dynamics (CFD) simulations to ensure good gas flow in the nanotube/nanofiber cooler structure.

First prototypes of test chips and packages with CNT cooling devices

Here we dealt with the cooling effect achieved for silicon and alumina based functional chips developed by UOulu at WP2.

We have used direct growth and also post mounting techniques. Sparse and dense films as well as microstructured coolers using pre-patterned growth or laser processing were tested with various speed of coolant gas flow. The cooling geometry was derived from the simulation results, where computer simulations predicted the optimal fin number and spacing. Besides the Chemical vapor deposition (CVD) system, we have also employed the new Plasma-enhanced chemical vapor deposition (PECVD) system at UOulu.

Table 1. Cooling efficiency measurement results on alumina test samples performed with various forced cooling air gas flows.

air flow (l/min) 0.0 0.5 1.0 1.5 2.0
temperature without heat sink 100 73 66 59 58
temperature with CNT heat sink 100 68 58 54 50
temp. difference (°C) 0 5 8 5 8
cooling efficiency (%) - 6.8 12.1 8.5 13.8

For the first prototypes the cooling performance was limited but still well measurable.

Second generation test chips and packages with integrated CNT cooling devices

The integration of CNTs into existing technologies used in electronics was successfully demonstrated. The 2nd generation ceramic test chips showed better performance than 1st generation counterparts. This is mostly due to i) better thermal interface between the cooler and the electrode due to better soldering process, and ii) better cooler geometry for forced air cooling, i.e. bigger fins and gaps between fins which yields to better air flow inside the cooler and consequently enhances the heat removal.

The thermal interface between the cooler and the substrate (electrode) plays also a key role for efficient cooling performance. Our soldering process was optimized for this purpose (comparison measurement with different pressing time) resulting in better performance than with 1st generation test chips. The results indicate also that the cooling performance of CNT-based cooler is comparable with its reference counterpart made of copper.

We have compiled a report on guidelines for CNT/CNF growth being compatible with Si and ceramic packaging technologies

An example provided in this report:

Figure 9. Original process for CNT soldering from “Chip cooling with integrated carbon nanotube microfin architectures”, K. Kordás et Al., Applied physics letters (2007), 90 (12).

Figure 10. Design and fabrication process of the interface-enhanced CNT microfin on-chip cooling system, by Chalmers. Image is taken from “A complete carbon-nanotube-based on-chip cooling solution with very high heat dissipation capacity”, Yifeng Fu et al., Nanotechnology (2012), 23

The selected technologies are ideal, since they can be scaled up with relative ease. In the final part of the project we demonstrated that the post mounting process using real life silicon chips and also 2” wafer size carbon nanotube growth.

WP 5 Post-mounted CNT coolers on chips and packages


In WP 5 lead by the Chalmers team, we demonstrated CNT coolers that are post-mounted on the chips and ceramic packages. Imprint transfer technology of aligned CNTs (which are grown at high temperature) onto thermally sensitive substrates (e.g. PCBs) at low temperatures using isotropic and anisotropic conductive adhesives were further developed. Different patterns of CNTs were be applied in the transfer process to create structures of cooling fins. Growth of CNTs in high aspect ratio silicon vias and the planarization of this structure were also be studied.

CNT cooling structures assembled by transfer process using conductive adhesives

The focus of this work was to develop materials and processes to transfer and form CNT cooling structures at low temperature from their original growth substrates to the surfaces of silicon chips or packages where cooling are needed.

This deliverable included three major parts. We presented a comparison study of different assembly materials for vertically-aligned CNTs (VA-CNTs). After that the progresses on CNT cooling structures assembled and formed by conductive adhesives were reported. That last part we described the development work of CNT-filled conductive adhesives.

These results suggest solder as the best candidate material if low contact resistances are needed. On the other hand, isotropic conductive adhesive (ICA), an anisotropic conductive adhesives (ACA) provide better mechanical strengths while ICA can still produce acceptable contact resistances. ACA delivers highest contact resistances among the three materials and its major advantages are its easy handling and short processing time.

CNT structures assembled and formed by conductive adhesives have been demonstrated. Because the CNTs are aligned parallel in the film and only attracted to each other by weak van der Waals forces, they are easily separated by applying external forces. The transfer of CNTs and the formation of CNT patterns are achieved simultaneously. Therefore there is no need to use photolithography to pattern the catalyst layer.

The thermal conductivities of composites containing different types of CNTs were investigated. The incorporation of CNTs into polymers resulted in enhancement of the thermal conductivity compared to Ag-filler. Since the thermal conduction in CNT is by phonon transfer, the nanometric size and the huge interface lead to strong phonon-scattering at the interface. Thus, a relatively low interfacial area, weak interfacial adhesion promote the conduction of phonons and minimizes coupling losses. According to this, the non-treated MWCNTs seem to have the highest potential to improve the thermal conductivity of epoxies.

Results on stacked silicon chips connected by CNT-filled through vias and on solder mounted CNT coolers

The motivation of this research was to explore and examine the possibility of utilizing CNTs as an interconnection material in 3D integration. It has been widely expected that the continuous size miniaturization and performance enhancement in the future will be mainly driven by the progresses of integration technology rather than shrinking the feature size of transistors. The unique electrical, thermal, and mechanical properties of CNTs make them an attractive solution to meet the challenges of miniaturization, thermal management, and reliability in future highly integrated electronics.

The measured bulk and contact resistances of CNT-TSVs in the present work are compatible with reported results for CNT forests or films, but the CNT-TSV values are still not as good as those obtained for Cu-filled vias. On the other hand, the results are competitive to at least one existing technology on the market using polysilicon as the via filling material. Nevertheless, since the development of CNT-TSVs is still in its infancy, there is still much room to improve the conductivity of the CNTs by a number of different measures, such as optimizing the growth, post-growth high temperature annealing, and doping.

Despite the higher resistances compared to metal-filled TSVs at this stage, the CNT TSVs have a number of attractive advantages. First, the technology shows good manufacturability. Filling TSVs with CNTs is easier and the process much faster than that with electroplating Cu. The growth of CNTs in TSVs in our work only took 1.5 to 3 min using the LP-TCVD process. In the case of post-growth transfer of CNTs into vias, the processing time is also quite short (~2 min). Deposition of the catalyst layer for CNT growth can be easily done by standard evaporation. On the other hand, high-quality electroplating of Cu in deep TSVs needs deposition of a continuously uniform seed layer. This process itself is a highly demanding and challenging task. Furthermore, the interconnection scheme shows great simplicity of implementation. The CNT TSVs can be easily interconnected by simple mechanical fastening with the extended parts of the CNT forests acting as bumps.

The soldering of CNTs into ceramic substrates was successfully demonstrated. Both large area (3x3 mm2) and small area (array of 200x200 µm2 fins) CNT films were successfully soldered on ceramic (alumina) test chips. The soldering process was optimized for getting best possible thermal interface between the cooler and the substrate without using an excess amount of solder and without damaging the original CNT film. In principal, very small amount of solder is needed for successful soldering with the method used. Moreover, the method used is damaging the original film very little (both large and small area fins) making the integration of CNTs into ceramic electronics assemblies feasible. The resulting device has both good mechanical and thermal contact in between the cooler and the electrode. All in all, the method introduced here demonstrates that CNT integration into existing ceramic electronics technologies is really possible for tomorrow’s applications, like chip cooling with CNT-based cooler structures.

WP 6 Thermal measurements


In WP 6 we analysed and optimized the heat transport properties of the carbon nanotube based cooler architectures defined and fabricated in the previous work packages. Periodic thermal excitation method using Peltier heaters and thermocouples were employed to measure bulk as well as interfacial thermal resistances of complex architectures used in the assemblies. In addition, a more accurate method (3ω) was adopted which used pulsed laser heating instead of Peltier heaters.

Heat transport calculations

The THEMA-CNT consortium has performed a detailed theoretical modeling of the thermal transport properties of carbon nanotubes and utilized three different thermal property measurement systems (SHT, Oulu, SzTE) for assessing the properties of the as-grown carbon nanotube forests and the CNT-containing adhesives synthesized by the partners. The most promising results achieved so far are related to the CNT/Ag composite epoxy resin thermal adhesives, however, even these figures need to be improved still. Concerning the thermal conductivity of carbon nanotube forests, it proved to be difficult to measure experimentally and was found to be below our original expectations. On the other hand, it is important to realize that the primary goal of the THEMA-CNT project is to develop cooling solutions for power electronics. In that respect, the thermal conductivity of any sample should only be considered as one indicator that can help is predicting the efficacy of the final cooling solution.

It has been established in this WP that the carbon nanotube based cooling solutions are suitable for chip cooling applications. It has also become clear that the type of the interface between the nanotubes and the final thermal reservoir media plays a crucial role in the cooling performance of the system.

WP 7 Multi-scale modeling


In WP 7 the UPV/EHU group performed molecular dynamics simulations of phonon transport through interfaces. The group combined the use of first-principle numerical codes (Octopus and Self) for average size simulations (less than 500 atoms) with classic molecular dynamic codes (as NAMD) for huge systems. The phonon transport calculations were done through a non-equilibrium green function (NEGF) formalism code, similar to the NEGF code that we have used previously to calculate the electronic transport properties in nanotubes for SANES project. The group had access to five Beowulf clusters (with over 400 processors and estimated peak of 3.4 Teraflops) and the Barcelona Supercomputing Centre where computing time is allocated to the group’s activities.

The modeling of the dissipation of the heat through CNTs in chips

It has been divided in three stages: 1) Intrinsic heat transport in realistic CNTs (i.e. CNTs with defects). 2) Heat transfer from a solid interface (the chip) to the CNTs. 3) Heat dissipation from the CNTs to the air. The main conclusion of the stage 1) is that defects affects strongly to the heat conductivity in CNTs and can reduce their ideal heat conductivity (the one for a pristine CNT) one order of magnitude (for a CNT with 1 defect per 1000 C atoms). The main conclusion of the stage 2) is that the leaks in the heat transport between a solid interface (the chip) and a CNT are due to the mismatching of both structures and not to the composition of the solid interface. Two posctdoc researchers have performed the simulations corresponding to stages 1 and 2 using the Barcelona Supercompution Center resources and the Beowulf Cluster. All these calculations have been carried out at nanoscopic scale (few hundred of atoms), being possible to use high accuracy first principles techniques.

As shown, CNTs are excellent thermal conductors. In general, the presence of an interface results in a degradation of the thermal transfer properties of CNT. We carried out an extensive classical molecular dynamics simulations were performed to understand the interfacial transfer of heat between a carbon nanotube and air. To this end, we investigated computationally a 400 Å long (10, 10) CNT immersed in a large bath of explicit air molecules. We monitored the time evolution of the temperature of each subsystem under non-equilibrium conditions. The unit cell was filled with varying amounts of air molecules (a total of 1600 and up to 16000 air molecules were used) to elucidate the effect of pressure of the heat transfer across the interface. We have unambiguously shown that higher air pressures lead to more efficient heat dissipation from the nanotube. From the analysis of the vibrational density of states, we conjecture that oxygen molecules may be more effective in this dissipation process as they exhibit strong overlap with the vibrations of the nanotube (G-band mode). Finally, from virtual temperature jump experiments, we estimate that the system at 10 atm is about 9 times more efficient at dissipating heat than the system at 1 atm, consistent with the ideal gas behavior. Thus, our MD simulations have convincingly shown the role of gas pressure on heat dissipation from CNT and the effect of an interface with air on the thermal transport properties.

WP 8 Implementation of CNTs onto CMOS technology - demonstration of large scale processing


WP 8 lead by University of Oulu utilized the know-how we gained in all previous work packages during the project. WP 8 aimed at producing chips with CNT coolers on 2” wafers, which could be the stepping stone for the large scale fabrication of electrical devices..

According to previous WPs the MWCNTs grown by catalytic chemical vapor deposition are the most suitable for post-mounting. Thus, a 4” inch CCVD system for 2” inch samples has been built in UOulu. On Semiconductor along with IMEC provided dummy and functional chips on which the MWCNTs were soldered on 2” scale and after post-mounting IMEC measured and verified the functionality of the chips as well as the cooling performance.

Figure 11. CNT arrays for post-mounting on functional chips

The transfer yield for large scale transfer was typically around 85 to 90 %. In the best case the yield was as high as 95 %.

Figure 12. CNT post-mounting process for functional chips.

Two different test chips were produced that can be used for thermal measurements. First of all there is the analogue test chip, with a heater and underneath this heater a diode that can be used to measure the temperature. The second test chip, is completely digital and on this chip there are 900 P-type temperature sensors and 18 DRAM heaters. This last chip needed a custom build measurement set-up to measure and drives the chip, while the first chip could be used and measured using more common equipment.

The measurement results clearly show a difference between the chips without and with CNT pillars mounted when cooling. Using the vertical cooling set-up, the improvement in temperature using chips without CNT’s is between 11 and 17%, while for chips with CNT’s this is between 16 and 24%. Using the horizontal set-up even makes a clearer difference: the improvement using non-CNT chip is between 11 and 20%, while for CNT-chips this is between 25 and 36%. There is also a difference in improvement or efficiency between higher and lower current, but this is logical as higher currents and resulting higher temperatures can be cooled more efficiently than lower temperatures. Also the difference in cooling between the vertical and horizontal flow can be explained easily: the vertical flow of air is stopped by the chip and creates a lot of air agitation around the CNT and cool the chip in this way. The horizontal flow will remove the heat more easily as there are almost no obstructions and the airflow is not disturbed.

CNT transfer yield of 100% could be reachable with the use of proper automation and alignment tools and with tailored chip layout. Performance of solder in this project (adhesion and wettability) is superior compared to previously used solders.

All in all, the feasibility of large-scale synthesis and solder transfer of CNT structures on silicon chips (actually, on any proper substrate) was demonstrated. The transfer yield of the used transfer process was remarkably high, taking into account that it was done totally manually. The whole CNT transfer concept was possible to be done using traditional equipment and methods. Moreover, the CNT structures did not suffer much of damage during the transfer. These findings give a promise of up-scalable process for future’s applications related to CNTs.

WP 9 Component reliability

In this work package, we focused on component reliability research of the assembled cooling structures. The ultimate goal was to acquire information on possible failure mechanisms in the novel devices, and in turn provide solutions for improving reliable device performance and extended lifetime both vital in exploitation and commercialization of new technologies.

Thermal and mechanical testing of components with direct growth of CNTs/CNFs and post-mounted CNT coolers

We carried out an extensive study mechanical and thermo-mechanical performance of direct growth and post mounted CNT coolers both from simulation and experimental tests.

The motivation of this part of work is to have a better understanding on how the thermal performance and reliability of CNT cooler is influenced by mechanical (different air jet impingement) and thermo-mechanical (thermal cycling) tests. The prediction of failure and failure analysis was also carried out.

Figure 13 Finite element model of CNT fin on silicon by indium solder alloy.

We found that the solder thickness has positive effect on the thermo-mechanical performance, while the CNT fin height has negative one. So for designing CNT fin on silicon connected by soldering experiment, it was suggested longer CNT fin should be connected by thicker solder for better reliability.

Performance and Mechanical Reliability of CNT Fins for Micro-Cooler

The in house built test system was mainly composed of the air jet system, heating devices, data acquisition systems, and infrared camera, as shown in Fig. 14. The jet was issued from a round nozzle of 1mm in diameter located right above the sample center. The jet flow was controlled by a micro-flowmeter. An infrared (IR) camera provided non-contact temperature measurement with a resolution of 0.03oC.

Figure 14. Sketch map of the testing system.

We observed that the surface temperature of the sample decreases dramatically with the introduced jet impingement, and the color on the CNT fins also changes. When the surface temperature becomes steady, the value changes from 42.8oC to 35.2oC with a 17.8% decrease in magnitude.

The CNT cooler together with an air jet impingement can provide a potential option for effective heat dissipation for high-powered chip/devices. An experimental investigation has been carried out by establishing a testing system to study the mechanical and thermal properties of the CNT fins. The IR measurement verifies the validation of the CNT fins with an air jet as an effective cooler method. The fins show quite good strength when the jet impingement loading is low. With increasing the air jet loading, some of CNTs start to decline at the root of the CNT boundless. Furthermore, a numerical simulation has also been conducted to study the influence of the fin heights on the heat transfer properties of the micro-pin-fin cooler with an air jet. It is found that the increasing fin height, the jet air will penetrate more deeply into the spaces between the fins, and this phenomenon could cause the failure at the root of CNT bundles.

According to the thermal characterization and reliability test, we concluded that the CNT based micro cooler shows very high thermal dissipation capability, due to the low interfacial contact resistance, the high thermal conductivity of CNTs and the high surface/volume ratio of CNT micro fins. Reliability test is performed on the as-fabricated demonstrator, 500 thermal cycles have been carried out between 20 ˚C and 85 ˚C. Results show that its cooling performance is slightly degraded after 300 thermal cycles, but it becomes stable and still works efficiently after 500 cycles.

WP 10 Environment issues


In WP 10 lead by SzTE, a systematic collection and analysis (TEM, Raman) of laboratory dust was made to evaluate the level of CNT contamination caused by the synthesis of nanotubes in the participating laboratories. In addition, we investigated the CNT emission from cooler devices upon usage. The acquired data will help us evaluating the real hazard of working with and using CNTs. In turn we work out safety protocols for producing, handling and using carbon nanotubes in the laboratory and in households.

Developing the CNT measurement methodology

We studied the known health issues of carbon nanotubes and reviewed the most important national and European regulations and standards related to airborne nanoparticles and human health. It was followed by a review of the commercially available (nano)particle measurement instruments and the special requirements of identifying carbon nanotubes among other ambient dust components. Finally, we have discussed the advantages and disadvantages of active and passive air sampling units for THEMA-CNT use and decide in favor of passive samplers. A detailed air sampling protocol was defined and the governing principles of passive CNT sampler placement were given. CNT emission sources and suggested air sampling points were identified.

The following CNT measurement protocol has been established in this deliverable for THEMA-CNT partner air monitoring:

1. Identify CNT emission sources at partners.
2. Define sampling locations.
3. Place passive air sampler units at the selected locations.
4. Do not touch until end of sampling interval (tentatively 3 months).
5. Send complete sampler unit back to SZTE for analysis.
6. Remove ¾ of filter for analysis. Preserve ¼ part intact for future cross-reference.
7. Take a series of SEM images of sample surface. Randomly chose 3 points in each filter quarter, record 5 images at x10k magnification in each spot. Count the CNTs and average over the 3x3x5=45 images.

Dissolve the cellulose nitrate filter in acetone. Mix the solution with a predefined amount of silicone oil, evaporate the acetone and measure the d.c. conductivity and the dielectric relaxation properties of the silicone oil solution. Compare against known calibration standard for CNT concentration.

CNT levels in all participating groups’ laboratories were monitored during the entire length of the project were monitored. We have concluded that even the vicinity of the CNT production reactors, finding airborne CNTs is minimal; therefore the technology can be considered having minimal risk for humans and also low risk of contaminating the silicon processing.

The University of Szeged has constructed two measurement setups for this work package. The first one was an unsupervised mode air sampling device which was distributed to all partners. The replaceable carbon nanotube trap of this device was regularly analyzed the Szeged team. These measurements have confirmed that carbon nanotubes are not present in any detectable quantity in normal office air or in laboratory air where proper venting and air filtration protocols are operated. On the other hand, carbon nanotubes were detected in the atmosphere of a laboratory where no proper venting was installed and the sampling unit was operated next to a carbon nanotube production furnace.

The second measurement setup constructed to measure the release of carbon nanotubes from thermal management products created by the THEMA-CNT network partners. Thermally conductive adhesives synthesized by SHT and chips with direct-grown carbon nanotube cooling forests synthesized by Oulu were tested. The signals of the setup operated with and without a carbon nanotube containing sample were practically identical. Therefore, we conclude that neither the SHT adhesives nor the Oulu chips would increase the risk of human exposure to carbon nanotubes if these devices were actually incorporated into commercial thermal management solutions.

Potential Impact:

Strategic impact

The new knowledge acquired during this research expected to lead to the large-scale exploitation of carbon nanotubes in cooling applications with performance better than their conventional competitors. Because of the importance of the topic and the large size of the corresponding electronics market, the outcomes of the project have enormous market potential. High-performance electronics used in our daily life (portable telecom devices, satellite systems, military applications, etc.) demands efficient cooling components, therefore direct implementation of the results might be possible and could contribute to new companies evolving in the co-operating members’ countries.

In order to bring about the above impacts, the following steps were accomplished: (i) successful integration of carbon nanotubes in electrical devices, (ii) cost-effective and feasible technologies that are scalable to be utilized, (iii) safe and practical protocols for processing and handling of carbon nanotubes and (iv) rapid product/technology development.

The project was accomplished in a synergic collaboration with several European and a supporting partner from the US (Rice University, Houston). The research carried out was highly interdisciplinary involving chemists, physicists, electrical engineers of universities and research organizations as well as the expertise of market players represented by an SME and a multi-national industrial partner. Due to the complex nature of the project, it was evident that it would be inefficient and unprofessional to try to solve it within one laboratory/institute or even within a single country. In addition, the potential relevance of nanoelectronics and the industrial implications clearly pushed the subject beyond national frames, thus requiring both scientific and economic support at the Community level. Establishment of a close link between leading laboratories within Europe resulted in a substantial scientific benefit with strong influence on the economic and political goals of the EU. This focused scientific effort, coupled with the opportunity to train a number of young researchers in excellent academic and industrial laboratories could lead to an increase in the number and quality of top level European scientists and thus reduce the scientific, technical and economic dependence of Europe on other countries such as the USA and Japan.

The project is strongly linked to other projects being accomplished on national level (Nano-Therm CNT, Academy of Finland). Each partner had several projects (National Academies, Industrial R&D, etc.) that addressed smaller segments of this project and thus supported our joint effort.

The expected results of the project will be generic and can be applied in a versatile manner. External factors, such as the change of the current main technology platforms would not influence significantly the applicability of cooling with CNT based architectures. Moreover, because of the increasing chip/package component densities and the accompanying high power demand, better and eventually new cooling concepts will be needed otherwise the electronics industry cannot progress with further component improvement/development. The European silicon industry (and electronic as a whole) needs novel technologies to challenge US, Japanese, and South Korean competitors. Our project is targeted this very sensitive and important segment of electronics, and proposed a number of different scalable solutions for thermal management of electrical components at various packaging levels using integrated coolers based on carbon nanotube architectures.

By providing feasible and scaleable technologies that successfully solves the difficulties of component cooling, using the results of this project, the European industry and SMEs could immediately gain advantage against their US and Asian competitors.

Strategic motivation of the project

Electronics have become more and more important in today’s human lifestyle. Today hundreds of new applications have found a way in order to make the life more comfortable, safer, more secure and more ecological. The environment where electronics are used, the way electronics are produced (smaller, faster, cheaper, new materials) have evolved. First the emphasis was put on getting things faster, later high voltage became important, followed by high current applications. Low cost and high degree of versatility comes always into the picture. This can be achieved by introducing more advanced technologies with increasingly smaller dimension.

The industrial end-users of the technology developed in the THEMA-CNT project can be clearly identified: our primary targets are high-tech electronic companies involved in component production as suppliers for the automotive, aeronautic and safety industry manufacturers. One such end user SME (SHT Smart High-Tech AB referred in the proposal as SHT) participated in the project effort and carried out testing of working prototypes/demonstrators of THEMA-CNT project. The other potential end-user is ON Semiconductor Belgium had an active role in developing and scaling up integration of CNTs in electrical devices.

ON Semi has a large market segment in automotive and industrial electronics. To maintain leadership in this market segment it is required that ON Semi keeps track with latest challenges and developments in automotive and industrial electronics. Regulated Alternator Concept, Printer drivers, Solenoid drivers for controlling the valves of the hydraulic ABS systems are a few examples where these new developed devices will find application.

As for SHT, the main motivation was to gain sufficient knowledge on reliability of the novel devices. Component reliability is an essential factor in business to hold existing and get new customers as well thus enabling to expand the company and to acquire new market shares.

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