Objective
In our approach we will focus on three areas of development:
- Technology: To explore new technologies which have the potential for realising the Coulomb blockade at room temperature, by investigation of nano-fabrication with Scanning Probe Manipulation and conducting polymers. To develop multi-layer processing for Coulomb blockade circuits.
- Components: To develop component design concepts, by pushing forward the performance of components used for interfacing Coulomb blockade circuits with conventional semi-conductor circuits. To investigate new concepts for background charge-insensitive Coulomb blockade devices.
- Complex circuits: To study complex circuits involving several Coulomb blockade elements. To build up a library of digital circuits and to investigate their use in logic and memory applications.
Development tasks are aimed in one of two basic directions: A reduction of feature size and development of well controllable methods for realising Coulomb blockade at higher temperatures, and application of presently well controlled methods to develop circuits of greater complexity. Progress in these two directions is essential for the realisation of real applications in the electronic industry, such as digital logic and memory circuits with very high packing density.
The Information Technology (IT) industry faces many daunting technological problems in the design of future electronic circuits. Several of these problems centre around the need to implement device function with increased density on chip, lower power consumption, and simpler design. The design concepts used in conventional semiconductor technology cannot be scaled down indefinitely, and thus new concepts must be found. In recent years, physical transport properties based on the Coulomb blockade of tunnelling of single charge quanta (Single Electron Tunnelling, SET) have come to light as a possibility for implementing electronics ("single electronics") at the nano-metre length scale.
Single Electron Transistors may overcome the physical limitations of MOS transistors. MOS exploit the field effect described by classical transport equations for the charge carriers, and are thus limited by the finite length of space charge layers, tunnelling effects and fluctuations of the doping concentrations. The single electron devices exploit the Coulomb blockade in very small metallic capacitors, where quantum tunnelling through insulating layers is essential. Thus these devices can be made much smaller than MOS transistors. If room temperature operation is considered, typical capacitances should be in the range of 0,1 to 1 attoFarad, corresponding to feature sizes of 1 to 10nm.
The CHARGE project is a collaboration of several groups in Europe with a broad base of expertise and experience. The collaboration consists of partners from industry, academic and government laboratories. The purpose of this collaboration and the objective of this project is to investigate the theoretical and practical problems associated with using extremely small amounts of charge for the realisation of bits of information.
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Call for proposal
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CSC - Cost-sharing contractsCoordinator
412 96 Gothenburg
Sweden