During the last few years, exploitation of the ever-progressing fabrication technologies has resulted in increased complexity in electronics products and hence an increase in the cost of testing them. In certain areas this testing can account for up to half the product cost. This can best be solved by treating the design and testing of the new product as part of the same problem.
The EVEREST project aimed to provide a consistent environment for checking the testability of products while they are being designed, and for generating the data which will ensure that the designs can be verified before construction and that the fabricated parts can be easily tested for manufacturing faults.
Testing of electronics, specifically very large scale integration (VLSI) based systems, has hitherto been based on ideas and skills conceived and matured in the United States of America. However, the growing understanding of quality issues has focused attention on the need for promoting design for testability (DFT) and testing in general. Creation of a strong environment in the field of testing has been identified as a strategic necessity for Europe. The European vanguard efforts on research and engineering systems for testing (EVEREST) project is addressing this as follows:
by promoting the general use of a test specification format;
using expert systems for test purposes;
the designing and developing of tools for test generation;
establishing a general methodology applicable to DFT, self test and silicon compiler environments;
providing a VLSI verification tester.
An automatic built in tool for machine testing has been developed. Using a system of dynamic programmable logic arrays (PLA) with complementary metal oxide semiconductors (CMOS), we have developed specific techniques of design for testability which enable breakdown lists to be obtained.
A general study of the extension of the electronic design interchange format (EDIF) to include information to describe a test of an electronic product has been carried out. A data modelling methodology has been used to develop the test specification extension, with the result that the extension is well defined and can be used for the evaluation of other test standards.
The project developed a prototype VLSI Verification Tester for mixed-signal circuits and an integrated suite of CAD tools which can help to remove the bottleneck between CAD and CAT environments.
The most important targets were:
- a verification tester to provide a complete design-to-test solution for VBSs
- a CAE-ATE independent test specification format
- knowledge-based solutions for test planning and failure diagnosis at various levels
- tools for test generation, functional validation, test data analysis and fault simulation
- design for testability methods for a silicon compiler environment
- integration of all functions in a user-friendly workstation environment.
UB8 3PH Uxbridge
5656 AA Eindhoven
5600 MB Eindhoven