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Redistribution and activation phenomena in integrated circuit and device manufacturing

Objective

The RAPID project aims to achieve major advances in understanding and modelling of such non-equilibrium phenomena.

Up to now, development of process simulation models in Europe has been done in a largely piecemeal way. Academic institutions have typically focused in isolation on specific physical aspects, while industry has concentrated on modelling processes currently under development. Where industry has funded academic research, this has produced focused solutions that succeed at the point of delivery but do not address future (or other) technology problems. This cautious and pragmatic approach has limited the development of predictive models and simulation tools.

The project will avoid these limitations and bring together specialists in solid-state physics, materials science, and electronic engineering, with extensive experience in mathematical modelling and computer simulation, as well as processing and measurement of silicon devices. By a unique combination of experimental techniques basic physical issues on defects, diffusion and electrical activation will be addressed in a synergistic way, relevant to all future silicon-based devices. Based on these experiments, a physically motivated model will be developed and benchmarked against dopant profiles and electrical data of sub-micron devices. Key results from the project will be implemented into TCAD tools used by industry. This procedure has become feasible now that physics-based simulators such as SUPREM-4 are commercially available. In this way, RAPID will contribute to the reduction of times needed and costs incurred in the development of novel ULSI devices. Efficiency is further increased by shifting the effort on software development to the commercial suppliers, with appropriate safeguards on access to the models. This approach has been tried successfully by Philips and GEC, implementing models for defect-coupled diffusion and diffusion in polysilicon in SUPREM 4.

The continuous reduction of the lateral feature size in ULSI MOS transistors implies that various alternatives are tested and validated during device design, some of which involve bandgap engineering by silicon/germanium layers. A technological validation of all concepts suggested forbids itself because of the enormous financial costs as well as because of time being precious when persevering with maintaining leadership. Therefore, technology-computer-aided-design (TCAD) tools are extensively used by semiconductor companies during front-end development for preselection of options. Similar considerations apply also to development in bipolar technology.

The small feature sizes aspired imply also an extremely low penetration depth of source/drain profiles which can be obtained only by anneals with a low thermal budget. But even for such low-thermal-budget anneals, a rapid redistribution of dopants is usually observed due to point defects generated especially during ion implantation, but also during annealing in oxidising atmospheres and due to the strain in SiGe layers.As, device simulators cannot be used for predictive simulations when they are based on wrong dopant distributions, the success of TCAD depends crucially on the ability of process simulation to accurately simulate dopant profiles after annealing steps.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

FRAUNHOFER IAF
Address
Tullastr. 72
79108 München
Germany

Participants (4)

Centre D'elaboration des Materiaux et D'etudes Structurales
France
Address
Rue J. Marvig 29
31055 Toulouse 4
National Centre for Scientific Research Demokritos
Greece
Address
Patriarchou Gregoriou
153 10 Aghia Paraskevi
Nederlandse Philips Bedrijven Bv
Netherlands
Address
Prof. Holstlaan 4
5656 AA Eindhoven
UNIVERSITY OF SOUTHAMPTON
United Kingdom
Address
Southampton Ocenagraphic Centre, European Way
SO14 3ZH Southampton