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Novel paradigms for massively parallel nanophotonic information processing

Final Report Summary - NARESCO (Novel paradigms for massively parallel nanophotonic information processing)

In this research, we embarked on building a novel class of chips to process information. These chips are different in two ways from regular computer chips. First of all, they use light as information carrier, as opposed to electricity, which has a large potential in terms of speed and power consumption. Second, they use a novel brain-inspired paradigm called reservoir computing, which is related to neural networks. Also this helps with speed and power consumption.

Neural networks have been employed in the past to solve pattern recognition problems like speech recognition or image recognition, but so far, these bio-inspired techniques have been implemented mostly in software on a traditional computer. What we have done is implemented a small (16 nodes) neural network directly in hardware, using a silicon photonics chip. Such a chip is fabricated using the same technology as traditional computer chips, which opens the potential for cheap mass fabrication.

We have experimentally shown that the same chip can be used for a large variety of tasks, like arbitrary calculations with memory on a bit stream or header recognition (an operation relevant in telecom networks: the header is an address indicating where the data needs to be sent). Additionally, simulations have shown that the same chip can perform a limited form of speech recognition, by recognising individual spoken digits (“one”, “two”, …).

Further research has taken place on using this technology to improve the bit-error rate in optical fibre communication, as well as using photonic neural approaches to detect cancer cells in a stream of other blood cells, which are flown at high speeds through a thin capillary tube.