Final Report Summary - MOSILSPIN (Modeling Silicon Spintronics)
Growing technological challenges and soaring costs are gradually bringing conventional charge-based microelectronics progress to an end. Spin attracts attention as an alternative to charge as a degree of freedom for computations and non-volatile memory applications. Silicon, the main material of microelectronics, is attractive for spin-related applications as it is characterized by negligible spin-orbit interaction and zero-spin nuclei resulting in a long spin lifetime. Silicon is perfectly suited for building new spin-driven devices, as confirmed by recent impressive demonstrations of spin injection, propagation, and detection at room temperature. As the success of microelectronics has always been and is supported by smart Technology Computer-Aided Design (TCAD) tools, developing such tools for spin applications is paramount. The project objectives have been to create, test, and apply a simulation environment for spin-based silicon and silicon-compatible devices.
In order to design and fabricate high-performance spintronic devices, an understanding of spin transport and manipulation as well as injection properties in semiconductors is required. Addressing the behavior of the resistance as a function of the relative magnetization of the ferromagnetic source and drain in a silicon spin field-effect transistor demonstrated that the orientation of the silicon fin along the <100> crystallographic direction is preferred for silicon SpinFETs due to the larger effective mass and thus stronger modulation of the conductance as a function of spin–orbit interaction.
In contrast to charge, spin in a non-magnetic material gradually decays to its equilibrium zero value. Spin-flip processes due to carrier scattering and intrinsic spin-orbit interaction cause the spin lifetime to shorten, especially in confined electron systems. A microscopic model for spin relaxation, which takes into account the peculiarities of the silicon band structure and relevant scattering mechanisms, was developed. An accurate expression for the splitting between the subbands originating from the two opposite valleys was obtained. The dependence of splitting on the confinement potential (width and height), electric field, kinetic energy, and strain was investigated. It was demonstrated that uniaxial stress dramatically enhances the valley splitting. As the spin lifetime is mostly determined by intervalley scattering, shear strain boosts the spin lifetime significantly in silicon FETs. An additional spin lifetime enhancement was demonstrated for spins injected parallel to the gate oxide-silicon channel interface.
The spin relaxation matrix elements obtained with the microscopic approach were used to evaluate the spin lifetime with the ViennaSiSpin solver and included in a spin transport model based on the solution of the Boltzmann kinetic equation generalized to include the spin as a degree of freedom. A multi-dimensional deterministic Boltzmann transport equation solver (ViennaSHE), a framework for hull mesh adaption, volume mesh generation and qualification (ViennaMesh), a spin lifetime solver in thin silicon films (ViennaSiSpin), a support C++ library for handling meshes in arbitrary spatial dimensions (ViennaGrid), a library-centric finite element solver written in C++ (ViennaFEM), and a framework for generating and executing task graphs (ViennaX) are available.
Spin transfer torque RAM is promising for future universal non-volatile memory. The reduction of the switching current density and the switching time are the challenges. Our invention has been to use a magnetic tunnel junction (MTJ) with a composite free layer. The fast switching due to the peculiarities of the magnetization dynamics of the two parts of the composite layer was confirmed with the micromagnetic simulation environment based on the magnetization dynamics supplemented by the spin torque terms. The environment is being released as the open source tool ViennaMag, which was applied to investigate three-terminal magnetic memory cells and arrays.
Apart from memory applications MTJs can serve as elementary blocks of non-conventional logic-in-memory architectures. An implication (IMP)-based logic gate based on two MTJs with reduced error and energy consumption by about 60% was demonstrated. A new design of an IMP-based full adder involves only 27 subsequent FALSE and IMP operations, in contrast to 37 operations in earlier versions. Combining magnetic tunnel junctions with a common free layer allows the realization of a non-volatile magnetic flip flop. A universal non-volatile processing environment unit, consisting of a spin torque majority gate and several flip flops, allowing a realization of a full adder was proposed. By assembling several of these units in a grid a novel buffered magnetic simulation environment is envisaged. An ERC proof-of-concept project was recently granted to carefully check and implement these ideas.
In order to design and fabricate high-performance spintronic devices, an understanding of spin transport and manipulation as well as injection properties in semiconductors is required. Addressing the behavior of the resistance as a function of the relative magnetization of the ferromagnetic source and drain in a silicon spin field-effect transistor demonstrated that the orientation of the silicon fin along the <100> crystallographic direction is preferred for silicon SpinFETs due to the larger effective mass and thus stronger modulation of the conductance as a function of spin–orbit interaction.
In contrast to charge, spin in a non-magnetic material gradually decays to its equilibrium zero value. Spin-flip processes due to carrier scattering and intrinsic spin-orbit interaction cause the spin lifetime to shorten, especially in confined electron systems. A microscopic model for spin relaxation, which takes into account the peculiarities of the silicon band structure and relevant scattering mechanisms, was developed. An accurate expression for the splitting between the subbands originating from the two opposite valleys was obtained. The dependence of splitting on the confinement potential (width and height), electric field, kinetic energy, and strain was investigated. It was demonstrated that uniaxial stress dramatically enhances the valley splitting. As the spin lifetime is mostly determined by intervalley scattering, shear strain boosts the spin lifetime significantly in silicon FETs. An additional spin lifetime enhancement was demonstrated for spins injected parallel to the gate oxide-silicon channel interface.
The spin relaxation matrix elements obtained with the microscopic approach were used to evaluate the spin lifetime with the ViennaSiSpin solver and included in a spin transport model based on the solution of the Boltzmann kinetic equation generalized to include the spin as a degree of freedom. A multi-dimensional deterministic Boltzmann transport equation solver (ViennaSHE), a framework for hull mesh adaption, volume mesh generation and qualification (ViennaMesh), a spin lifetime solver in thin silicon films (ViennaSiSpin), a support C++ library for handling meshes in arbitrary spatial dimensions (ViennaGrid), a library-centric finite element solver written in C++ (ViennaFEM), and a framework for generating and executing task graphs (ViennaX) are available.
Spin transfer torque RAM is promising for future universal non-volatile memory. The reduction of the switching current density and the switching time are the challenges. Our invention has been to use a magnetic tunnel junction (MTJ) with a composite free layer. The fast switching due to the peculiarities of the magnetization dynamics of the two parts of the composite layer was confirmed with the micromagnetic simulation environment based on the magnetization dynamics supplemented by the spin torque terms. The environment is being released as the open source tool ViennaMag, which was applied to investigate three-terminal magnetic memory cells and arrays.
Apart from memory applications MTJs can serve as elementary blocks of non-conventional logic-in-memory architectures. An implication (IMP)-based logic gate based on two MTJs with reduced error and energy consumption by about 60% was demonstrated. A new design of an IMP-based full adder involves only 27 subsequent FALSE and IMP operations, in contrast to 37 operations in earlier versions. Combining magnetic tunnel junctions with a common free layer allows the realization of a non-volatile magnetic flip flop. A universal non-volatile processing environment unit, consisting of a spin torque majority gate and several flip flops, allowing a realization of a full adder was proposed. By assembling several of these units in a grid a novel buffered magnetic simulation environment is envisaged. An ERC proof-of-concept project was recently granted to carefully check and implement these ideas.