Making modern embedded systems faster and less power hungry by parallelization
Writing parallel programs has traditionally been considered a difficult task, even when parallelism is taken into account from the beginning. Moreover there is an urgent need to parallelize the massive amounts of legacy sequential code so as to increase its performance on processors and systems that refocus from single-thread acceleration to increasing the overall throughput. At the same time, memory (in particular cache) performance is essential to achieve the full gain from a parallelized application. However, while processor architecture tends to be relatively standard across applications within a domain, huge performance and power improvements can be achieved by tailoring the cache architecture to the application at hand, and not just to an entire domain.
The HEAP project faces these challenges directly, by developing:
1. An innovative toolset that helps software developers profile and parallelize existing sequential implementations by exploiting top-level pipeline-style parallelism.
2. A highly configurable cache architecture that can be tailored to an application by using the same profiling data as those that were used for parallelization, in order to fully exploit the available computing power.
When compared with the existing single-cache coherency architectures and the existing, mainly manual, parallelizing approaches, the end-product of HEAP (i.e. the novel architecture combined with the innovative toolset) is expected to: a) reduce the time for parallelizing sequential applications by 20% b) reduce the energy consumed for the memory coherency operations by 20% and c) increase the performance of the memory coherency systems by 20%.
The HEAP framework directly addresses two distinct multi-billion application areas (a) High Performance Computing and (b) Multi-core Embedded Systems. In both fields it is expected that the impact of HEAP will be significant worldwide; this claim is supported by the fact that the HEAP results will be internally exploited by two of the largest semiconductor companies in the world (STM and Thales), as well as a large scale Information Systems Provider (Singular Logic) and an SME (Synelixis). Moreover, the commercial version of the toolset will be exploited by two additional software tool-providers (ACE and Compaan Design). Moreover, HEAP-based multi-core systems are expected to help closing the digital gap in Europe, while mainly the open-source version of the toolset will reinforce European competitiveness in the areas of Parallelizing toolsets and the new innovative platforms will help extending existing service offerings to the EU citizens.
Call for proposal
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Funding SchemeCP - Collaborative project (generic)
14234 N Ionia