The aim of this project was to provide the basic knowledge and tools required to implement the boundary scan test (BST) technique and to incorporate it into IC and PCB design and testing. The use of BST will considerably reduce product development costs by improving test generation efficiency and accuracy and eliminating time-consuming and redundant steps in the development of a product.
This paper describes two built in self test (BIST) elements that have been designed using an hierarchical self-test concept in an Institue of electrical and electronic engineers (IEEE) 1149.1 JTAG environment. At chip level, a general self-test structure to implement the JTAG run BIST (RUNBIST) instruction has been chosen and the implementation of a macrocell to test embedded static random access memory (RAM) following this architecture is described. At the board level, a chip to test static RAM board array is presented. This chip is fully JTAG compatible, and it supports the RUNBIST instruction with the methodology previously described.
The purpose of this most successful project was to provide the basic knowledge and tools required to implement the boundary scan test (BST) technique and to incorporate it into integrated circuit (IC) and printed circuit board (PCB) design and testing. The use of BST will considerably reduce product development costs by improving test generation efficiency and accuracy and eliminating time consuming and redundant steps in the development of a product.
In the project there was developed, demonstrated and launched onto the world market a comprehensive range of BST testers, ranging from portable field test and diagnosis pods connected to laptop computers, add on units for logic analyzers, through to full scale production test machines.
The project partners have developed and demonstrated an embryonic board level test controller chip SISCO.
A static random access memory (SRAM) bank tester chip has been developed. The device enables the autonomous testing of large numbers of SRAM devices on system boards through the BST command loop.
The TIGAS chip has been developed within the project to enable the testing of complex and normally difficult to test logic clusters for BST-equipped system boards.
The BST-cell library implement BST on application specific integrated circuits (ASIC) will be marketed.
The boundary scan circuits description and data model format electronic boundary scan test (EBST), which is now incorporated into the international electronic data interchange format (EDIF), is available to all the project partners for exploitation. This work is fully compatible with the IEEE 1149.1 standard.
GATSBY is a boundary scan test pattern generation software package that will be marketed both as a stand alone package, as well as part of software support of production test machines.
A set of boundary scan test silicon compiler module generators compatible with the popular Genesil and GDT compile products of MentorGraphics has been produced.
The BSX1 very low cos t medium/low speed personal computer (PC) compatible plug in card (IEEE 1149.1 compatible), which can convert an ordinary PC into a bench top BST tester has been produced.
The final project demonstrator, BSX2, provides and ideal vehicle for the education of engineers in boundary scan techniques.
The project's work was based on IEEE Standard 1149.1-1990 on boundary scan test developed by the Joint Test Action Group (JTAG) and the P1149.1 Working Group.