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Embedded Reconfigurable Architectures

Project description


Embedded Systems Design
To develop an embedded system platform that dynamically adapt itself to the applications. The platform will be open-source: both the industry and academia can use it for fast design-space prototyping

The design of embedded systems such as mobile smartphones becomes increasingly more complex as multi-core processors are needed to achieve the required functionalities. This complexity has triggered the trend to move away from utilizing dedicated hardware designs to more general-purpose platforms. However, different applications such as the telephone and the camera functions in the mobile smartphone have different characteristics and requirements, making the efficient support of all these characteristics nearly impossible in the scope of a single fixed platform, despite its programmability. Consequently, we are observing the emergence of many-core chips, i.e. containing multiple but differently sized/performing/power-consuming processor cores. An example is the Tegra 3-chip from NVIDIA containing several high-performance cores and a low-performance/low-power processor core. Still, each core is not tuned efficiently for different applications.

The efficiency problem is addressed by the ERA project, which goals is to develop a platform that can dynamically adapt itself to the applications (characteristics and requirements) while taking into account performance and power constraints within its operating environment. We expect an increased performance of selected applications by 25% with the same energy consumption or reduced energy consumption by 30% with the same performance. Moreover, the ERA platform will allow for further efficient utilization of on-chip resources as the platform itself performs self-optimization and without much effort, the industry can use the platform to perform quick design-space explorations.

In a scenario where the complexity and diversity of embedded systems is rising and causing extra pressure in the demand for performance at the lowest possible power budget, designers face the challenge brought by the power and memory walls in the production of embedded platforms. The focus of the ERA project is to investigate and propose new methodologies in both tools and hardware design to break through these walls and help design next-generation embedded systems platforms. The proposed strategy is to utilize adaptive hardware to provide the highest possible performance with limited power budgets. The envisioned adaptive platform employs a structured design approach that allows integration of varying computing elements, networking elements, and memory elements. For computing elements, we will utilize a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores, and we will dynamically adapt their composition, organization, and even instruction-set architectures to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler exploiting the synchronicities between software and hardware. We strongly believe that having the complete freedom to flexibly tune the hardware elements will allow for a much higher level of efficiency (e.g. riding the trade-off curve between performance and power) compared to the state of the art. Finally, an additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems design.

Call for proposal

FP7-ICT-2009-4
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Coordinator

TECHNISCHE UNIVERSITEIT DELFT
Address
Stevinweg 1
2628 CN Delft
Netherlands

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Region
West-Nederland Zuid-Holland Delft en Westland
Activity type
Higher or Secondary Education Establishments
Administrative Contact
Linda Roos (Ms.)
Links
EU contribution
No data

Participants (10)