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Advanced x-ray photoelectron spectroscopy for high-mobility substrates

Final Report Summary - ASPECTS (Advanced x-ray photoelectron spectroscopy for high-mobility substrates)

Summary of the objectives:

The ASPECTS project is a Marie Curie fellowship funded by the European Commission in the Seventh Framework Programme (FP7). The two years project started in 2010 and pursued two main objectives.

In order to deliver the required performance, future integrated circuit technologies will need the introduction of novel semiconductor channels other than Si. For instance, the introduction of new materials in high performance transistors will allow reducing power consumption and increasing the speed of integrated circuits, whilst simultaneously reducing manufacturing and production costs. In this respect, one of the two objectives pursued by the project consisted in the definition of the best materials combinations for the gate dielectric stacks used on III-V semiconductor compound high mobility channels.

The main task towards the achievement of this objective was to acquire a comprehensive understanding of different semiconductor / oxide interfaces and gate stacks grown on high mobility substrates by molecular beam deposition. This was done by combining in-situ standard X-ray photoelectron spectroscopy data with data inferred from other state-of-the-art characterisation methods. X-ray photoelectron spectroscopy is a surface sensitive analytical technique which allows the determination of the chemical composition, thickness and some electronic properties of the different layers and their interfaces in a multilayer stack. By developing a fundamental understanding of the effects that different surface layers ('passivating layers') may have on III-V compounds, the project aimed at identifying a suitable combination of materials for the gate-stacks / channel regions and their integration in high mobility complementary metal-oxide-semiconductor devices. The goal was to obtain gate stacks with very high capacitance and low amount of electrical defects at the gate dielectric / semiconductor interface.

The other objective consisted in the assessment of a newly developed analytical tool for in-situ, angle-resolved X-ray photoelectron spectroscopy (AR-XPS). This type of spectrometer was designed to allow for the acquisition of angle-resolved data without tilting the sample. As such, it represented a very interesting technique for acquiring compositional profiles of multi-layered stacks grown on large sise semiconductor wafers (i.e. 8'). The performance of the system had to be carefully evaluated with respect to results obtained with similar and complementary analysis techniques and with other commercially available AR-XPS systems. This assessment had to be performed in direct contact with the company who developed the analyser with the clear goal of bringing hardware and software to state of the art. If mature enough, the angle resolved system would have represented an additional tool for the successful achievement of the other objective.

For the deposition of the dielectric gate stacks onto III-V compounds semiconductors, a ultrahigh vacuum chamber for the molecular beam deposition of oxides was used. The physico-chemical properties of the stacks and their interfaces were systematically monitored after each processing step, using the existing connected XPS system. Different substrate preparation methods prior to dielectric deposition, deposition paths, materials combinations and post-processing treatments were investigated. Complementary to the XPS measurements, other analytical techniques were employed to characterise the surface order and morphology and the overall structure of the deposited gate stacks. Electrical properties of the gate stack were inferred from capacitance versus voltage (C-V) and current versus voltage (I-V) measurements in capacitors, and from transfer and output characteristics measurements on transistors (drain current vs drain voltage, Id-Vd and drain current vs gate voltage Id-Vg). Finally, the chemical bonding, band bending and the valence band structure at the interface between In0.53Ga0.47As and the Si passivating layer was thoroughly studied using high resolution soft X-ray synchrotron radiation at TEMPO beamline at Soleil synchrotron and complementary measurements performed with the in-situ XPS lab source.

Introducing new gate materials at the required technology node requires the gate stack to have large capacitance (or low 'equivalent oxide thickness'). During the project, it became clear that gate stacks consisting in an amorphous silicon (a-Si) as interfacial passivating layer for the III-V surface in combination with an HfO2 high-? gate dielectric are limited in this respect. The maximum obtainable capacitance was limited by the formation of layers with low dielectric constant at the interface between the a-Si and the HfO2 gate dielectric during gate oxide deposition and high temperature anneals. In order to overcome this limitation, the unstable interface was modified by inserting a thin Al2O3 'barrier' layer between the a-Si and the HfO2. In combination with an optimised post-metallisation annealing, this thin Al2O3 'barrier' interlayer sharply reduced the a-Si interfacial reactions while preserving the III-V surface from oxidation. Owing to the presence of the Al2O3, gate stacks with excellent capacitance (EOT = 0.82 nm) were achieved on both GaAs and In0.53Ga0.47As substrates, and the gate stack was observed to be thermally stable up to 650°C. Excellent electrical characteristics were inferred from C-V measurements. Using the high-low frequency method on the CV curves, it was inferred that the density distribution of electrically active interface traps has a low midgap peak of 4*10^12 1/eVcm^2 for GaAs and of 5*10^11 1/eVcm^2 for In0.53Ga0.47As.

The gate stack grown onto an In0.53Ga0.47As/InP substrate was then successfully processed in field effect transistors following a 'gate-first implant-free' process flow which is compatible and similar to processes currently used in standard complementary metal-oxide semiconductor (CMOS) technology. The transistors performed well, with good effective charge carrier mobility values of 740 cm^2/Vs at high carrier concentration and a peak mobility of 1030 cm^2/Vs. Upon reducing the HfO2 thickness, the gate stack capacitance was further increased and the electrostatic integrity of the devices was even improved. A significant threshold voltage and flat band voltage shift was observed in the FETs with thinner gate stacks, which indicates the reduction of the amount of fixed charges in the stack. This had a direct impact on the effective charge carrier mobility, with an improvement of 23 % upon thinning the dielectric (peak mobility of 1270 cm^2/Vs). This was attributed to a reduced remote coulomb scattering.

These results represented a significant progress towards fabricating ultra-scaled CMOS-compatible III-V transistors and the evaluation of the performance of such devices. The introduction of III-V based devices onto a Si CMOS platform may have potentially a significant impact on the information technology industry by offering new functionalities and devices with improved performance but for lower power dissipation.

Finally, the assessment work done on the angle resolved XPS system developed at SPECS GmbH in Berlin helped during the different phases of the project in understanding the limits of hardware and software of such a tool. This led to the progressive improvement of the system which is now ready for installation at IBM premises and commercially available at SPECS GmbH. Since demand for this type of system is increasing, SPECS GmbH will largely profit from having this new product in its portofolio.