Final Report Summary - SKYFLASH (Development of Rad Hard non volatile Flash memories for space applications)
Executive Summary:
SkyFlash has been focused on the development of a strong rad-hard by design (RHBD) methodology for non volatile semiconductor memories to be used in space applications taking the best from standard CMOS (Complementary Metal-Oxide Semiconductor field effect transistors) submicron (180nm) silicon processes. The main ideas at the base of the project are the following: 1) development of rad-hard integrated silicon devices acting on the design more than on fabrication process; 2) application of non volatile memory technology (floating gate/floating trap cells) in space applications.
A key feature of integrated circuits destined to be used for space applications is that of radiation tolerance. Beyond the atmosphere (meaning in electronic equipment for satellites, probes or more in general spacecrafts) many particles (electrons, protons, high energy ions) collide with silicon devices releasing energy and possibly disrupt operations. There are two main effects of radiations on silicon devices: 1) long term effects (TID, Total Ionizing Dose); 2) short term and randomic effects (SEE, Single Event Effects).
Non volatile semiconductor memories in space market have been faced with old anti-fuse technologies till now; this means that media can be written (or burned) before the mission and only read during later on. This kind of device is called OTP (One Time Programmable) memory and is typically used for star maps or boot software storage and is the only one actually chosen by space market.
The real breakthrough for the introduction of programmable and erasable non volatile memories is the introduction of floating gate (or floating trap) memory cells.
Many problems arise on this well known technology since the ’60s but never used for rad-environments. The first one is the retention of the bit: a floating gate cell stores electrons in a sandwich of poly-silicon (or silicon nitride for floating trap, also known as charge trap) surrounded by silicon dioxide thus leading to a variable threshold proportional to the amount of electrons trapped; the exposure of the cell to an amount of radiations can move, during time, the threshold itself so changing the bit. Moreover, in terms of single events, an high energy particle can collide with a floating gate and if the energy is sufficiently high it is possible that trapped electrons can gain energy enough to migrate outside their traps.
It is worth mentioning that even if these aspects has been studied the technology and the methodology adopted were commercial: no efforts were dedicated to design a non volatile device to be rad-hard.
A non-volatile memory has other aspects that could be crucial for rad-environment: the circuitry for programming (state machines and program & verify algorithms), circuits for high voltage generation (typically a floating gate/trap cell need, to be written, a voltage more than double to power supply), circuits and algorithms for erase operations.
All blocks not directly related to non volatile memory cells and their organization in one or more arrays are generally called “periphery”. These blocks includes decoders, row and columns final stages, sense amplifiers for reading, buffers and high voltages part devoted to program end erase memory cells. If on side the memory cells must be stable in their retention job against radiations on the other the periphery must guarantee the right functioning avoiding degradation under TID and soft errors (and hard errors as well) when single events occur (SEE).
Since SkyFlash uses a standard CMOS 180nm process no dedicated processes are envisaged and for this reason all radiation hardening approaches are on focused on design only (Radiation Hardening By Design, RHBD).
RHBD methodologies previously developed by RedCat Devices in SRAMs has been extensively used in SkyFlash in combination with rad-hard charge pumps, high voltage distributions, band-gap references and basic logic to implement program and erase algorithm.
The final target has been the development of a 1Mbit reprogrammable prototype memory, single power supply, complete of all basic blocks required by all NVMs.
Project Context and Objectives:
The context addressed for SkyFlash project has been SPA.2011.2.2-02 Space critical technology and in particular ASICs (Support to existing 0.18 um technologies) for space application. This topics, as part of FP7 Space, has been faced also by ESA (European Space Agency) in several tenders tenders in the past (09.1QC.08 Reliability testing of commercial available flash memories (follow on from: radiation assessment of commercial flash); 09.1EP.02 Study of mitigation techniques/optimisation for analogue circuits in space radiation environment; 09.1QC.02 Radiation tolerant analogue/mixed signal technology survey and test vehicle design; 09.1QC.07 Technology assessment of dram and advanced memory products following in from radiation test and benchmark of commercial products against space requirements). The integrated circuits for space application scenario is quite peculiar; since silicon processes are large corporate prerogative it’s clear that these companies serve a very large market. All technological and scientific efforts are pushed to applications satisfying a consumer market, not a niche one. In this number we can include mobile phones, personal and notebook computers and so on. The benefits coming from a strong research in silicon processes for size reduction (transistors channel length) and enhancing performance (clock speed) give rise to more compact and more power final product (more and more small mobile phones with performance so high to include software applications for internet networking or e-mail management).
It’s clear that these scientific and technological efforts, following the well known Moore Law, are tracing a precise track in which there is only the consumer market.
Space electronics is a niche market but has also high-level requirements which basically are not satisfied by standard consumer electronics. These requirements, as explained above, are first of all the resistance to radiation but mechanical resistance (during launch) and thermal resistance too. Large silicon foundries, due to low volumes required by space market, are not appealed by these requirements and the result is a base technology which is not suited for space. The result is a technology lack.
Another aspect to be underlined is connected to the availability of some dedicated technology developed for military industry. In USA some silicon foundries (e.g. American Semiconductor) has developed silicon processes with a certain resistance to radiation and are involved in device design for military applications. The main problem related to such realities is that these players can only work for militaries and cannot provide either their components and their technology outside US: that’s called ITAR (International Traffic in Arms Regulations) which is a set of rules that control the export and import of defence-related articles and services. ITAR was activated during Cold War and reinforced more recently after September 11th 2001 and restricts all base technologies which can be used for weapon building including fighters or soldier equipment. The resistance to radiations is obviously considered and silicon processes for integrated circuits realised for military market fall under ITAR restrictions.
Space market and high energy physics market pay the drawback of this approach and the result, from silicon processes point of view, is that on one side basically there is a shortage of rad-hard technology and, on the other side, when a technology is developed it can fall under ITAR restrictions so becoming unavailable as well.
European Space Agency (ESA) and all European large scale integrators find difficulties in providing components and technologies for their production and this is the reason why they are pushing on ITAR FREE technologies, meaning a set of base and critical technologies which could be freely used by ESA members and their providers and integrators. ESA strongly aims to a base technology internally (meaning in Europe) developed which could not be included in ITAR or other restrictions.
Project Results:
SkyFlash project has been focused on the development of non volatile memories for space applications. It is worth to underline that the main issue is related to the single memory cell to be used to store the bit. Volatile memories, in fact, do not use any specific media but a very simple ensemble of standard transistors connected in a way to obtain a bistable circuit or, in other word, an elementary element to store the bit in its form of “0” or “1”. Without power supply the bistable element cannot store the data any more and the result is that data is lost: this is the volatile element. Non volatility is obtained by using more complex phenomena able to provide a state stable also without power supply thus moving the focus from the traditional electronic (or microelectronic) approach to the domain of physics.
Standard consumer non volatile memories (such as those used in USB sticks or as computer solid state hard drives) basically use so called floating gate or floating trap cells. The approach is very simple and is based on the insulation of poly-silicon (or nitride) by using silicon dioxide.
Silicon dioxide represent an almost perfect insulator and this behaviour guarantees the impossibility of any movement for electrons and holes (the counter part of electrons) even if it is better to say that movement can be obtained only at certain conditions and certain energies. A poly-silicon (or media) embedded in a silicon dioxide block represents a region where electrons can freely move inside such as a free chamber. The presence of trapped electrons in the chamber or their absence determines the bit status (poly-silicon or nitride filled of electrons represent “1”, the absence of electrons represent “0”) and this status may be detected thanks to capacitive coupling coming from the standard three terminals of a transistor. When power supply is removed electrons remain trapped in poly-silicon or nitride media and their energy is not enough to override the barrier represented by the surrounding silicon dioxide. They are like prisoners that cannot gain enough speed to escape from the jail and silicon dioxide are concrete walls.
Injecting electrons onto poly-silicon or nitride is not an easy task and taking them out is difficult as well. There are basically two methods based on two physical phenomena: the first is called Hot Electron Injection or, more commonly, Channel Hot Injection (CHE) and is based on a cascade of electrons flowing into the channel of a standard transistor. This cascade is provided by high voltages applied at the terminal of the transistor and has the target not to make flowing an high number of electrons but to give them enough energy to jump the potential barrier of the silicon dioxide and reach the buried floating gate (or floating trap); not all electrons will gain enough energy but this condition guarantees that some “lucky” electrons will be able to be injected. Channel injection is a quite rude to method to store electrons but has the great advantage to be easy to be triggered. On the other side the main drawback a the stress induced to silicon dioxide (prisoner-electrons can go in and go out but concrete silicon-dioxide walls are damaged time after time).
The second physical phenomenon used to store electrons is the Quantum Mechanical Tunnelling and it can be divided in two phenomena according to the thickness of the silicon dioxide. If the dioxide is thin enough an electron (at specific high voltage conditions) can be injected directly onto the floating gate or floating trap completely skipping the oxide layer; in this case we talk about Direct Tunnelling. With thicker dioxides the same operation can be obtained at similar conditions but electrons tunnel into the conduction band of the silicon dioxide where they can flow into the cathode represented the floating gate or floating trap; in this case we talk about Fowler-Nordheim Tunnelling. With Direct Tunnelling electrons are injected directly onto the chamber; with Fowler-Nordheim Tunnelling electrons are injected on the door of the chamber and then collected inside. Tunnelling is a method less rude than hot carriers injection thus leading to a lower dioxide degradation but from the manufacturing point of view it requires more sophisticated technologies lacking of reliability (in particular if the considered environment is hostile).
Floating gate (based on poly-silicon) or floating trap (based on nitride) are not the only media used for non volatile memories. Emerging technologies involving phase change, resistive or magnetic material are starting to be considered both for consumer markets and special markets such as space.
Phase Change Memories (PCM), also known as Chalcogenide Memories, are based on new material able to change their state from amorphous to crystalline under specific conditions. By heating these layers it is possible to obtain an hysteresis cycle that, at the end, provide a difference resistance where electron can flow. High resistance leads to a “1” and low resistance leads to a “0” (or viceversa according to the architecture used in the final application) and when power supply is over the phase of the material is not changed.
Resistive memories use the same approach but material are different; in this case layer containing hafnium oxide create a set of connection between different layer enhancing or reducing the overall resistance according to their number. Like PCM everything is played with higher or lower current but in this case it is a matter of nano-connections taking in communication different electrodes.
Magnetic memories are based on Tunnel Magneto-Resistance (TMR) which is a magneto-resistive effect that occurs in magnetic tunnel junctions (MTJs). This effect occurs in particular in ultra-thin (few nanometers) multi-layers of magnetic materials separated by a metallic (GMR, Giant Magneto-Resistance) or insulating (TMR) film. In the case of TMR, if the insulating layer is thin enough electrons can tunnel from one ferromagnet to the other and due to the fact that this process is forbidden in classical physics the tunnel magneto-resistance is strictly considered a quantum-mechanical phenomenon.
The above mentioned emerging technologies pay the drawback of the low maturity respect to floating gate and floating trap memories which are running since the ’60 and maturity, together with reliability, is one of the key assets for space electronics.
SkyFlash Project has been focused, according to technological independence request coming from the call, on the development of a roadmap concerning non volatile memories starting from the most reliable option actually available and represented by nitride memories.
Nitride and poly-silicon memories are very similar in the basic principles and also in the manufacturing flow but the first is an insulator while the second is a conductive material. Electrons injected in a poly-silicon media can still move inside while in nitride they are frozen in a specific location. In the floating gate it is not possible to determine the position of the charges, in nitride they are located in a cloud exactly in the position where they have been injected and according to their status the probability to be extracted by the media is lower in consideration of the fact they have less probability to gain enough energy to escape.
For the above mentioned reasons SkyFlash has considered nitride devices that, specifically, has been S-Flash (Sidewalls Flash) cells and CEONOS (Cost Efficient Oxide-Nitride-Oxide Silicon) both coming from a background properties of Tower Semiconductor. It is clear that the approach followed by SkyFlash is inclusive and not exclusive so the major part of the solutions can be moved also to floating gate memory cells or different kind of cells including PCM, resistive and magnetic.
The SkyFlash Roadmap has been based on Radiation Hardening By Design which is the main pillar in combination with a mature and reliable technology such as a standard 180nm CMOS process and a relevant experience coming from the major part of the partners in the field of rad-hard SRAMs.
The background expertise has played an important role also in the field of testing under irradiation. As well known to those skilled in the art microelectronic device design is very closely related with testing and when the final device is expected to be rad-hard this relation becomes stronger. Testing a rad-hard component is not an easy task; first of all tests must be done on Earth and the same conditions must be reliably reproduced. Moreover, in particular for total dose irradiation, tests must be accelerated because the effects in space spreading in a time line of years must be reduced to days in Earth. So, total dose, two aspects must be considered: 1) reproduction of space environment on Earth; 2) accelerated test to avoid expensive and time consuming procedures. Keeping these aspects under control means having in the consortium the necessary expertise and this is the reason why SkyFlash Consortium, even if the project has been heavily focused on the design, has decided to include partners devoted to total dose irradiation and not making use of subcontractors. The commitment on testing has been one of the pillar from the management point of view.
Single event testing may be considered in some ways more “reproducible” on Earth compared to total dose. Charged particles may be the same as in space and considering the fact these events are stochastic all issues related to accelerated tests are not an issue. On the other hand the equipment is more complex and difficult to be taken under control. If in total dose Gamma Ray and X-Ray chambers irradiation is delivered in conditions to be taken strictly under control from the point of view of the dosimetry (not to high because the test may be not in line on what happen in space and not to low to avoid long test) on the other hand with heavy ions and protons linear accelerator must be used and the complexity of such machines is relevant. Moreover the beam (heavy ions with xenon, nitrogen, or other) must be carefully prepared in terms of fluence, dimension of the window and, last but not least, Bragg Peak release. Since the effect is the release of energy it is important the maximum of energy coming from charged particles is not release in the back end of line (BEOL) of the chip were metals only interconnect transistors but in front end of line (FEOL) or, in other words, were transistors are manufactured and were the beam can really give a soft error or an hard error to the chip. Release the peak of energy in the exact position in depth of the chip is not an easy task and, again, this is the reason why SkyFlash consortium has decided to include as a partner, instead as a subcontractors, the required actors. For protons the same consideration are valid and SkyFlash Consortium has indeed produced a significant advance in testing also in the field of cross relations between total dose and single event effects enlarging the roadmap also in the field of testing.
As deeply discussed during the final meeting at the presence of the project officer and the technical reviewer, SkyFlash project has tested several parts under protons considering on one hand the possibility of soft errors (upsets) but on the other hand, thanks to the nuclear effect coming from the collision of protons producing secondary irradiation, also the degradation in terms of total dose. In short words SkyFlash has evaluated not only soft errors tout-court but soft errors when the component is fresh and when the it has been degraded by total dose. This is something ESA is carefully considering as well stated in ITT 7751 (Total Ionizing Dose Influence on the single event effect sensitivity of active EEE components) and this tells that SkyFlash has in some way anticipated a general need coming from the space community.
SkyFlash roadmap for the development of rad-hard non volatile memories has considered several aspects of whole. From the architectural point of view many assumptions came from rad-hard SRAMs but, as a matter of fact, the memory array is quite different thus leading to different effects when the device is irradiated. In non volatile memory cells bit upsets coming from the impinging of a charged particle is not an issue because the bit is not stored in a bistable element but in a single transistor having one state only. This does not mean that in a non volatile memory upsets cannot occur but that they are more probable outside the array in the periphery or in the output buffers taking the data outside the chip. This simple statement led to a very peculiar architectural approach relevantly different from the one adopted by standard non volatile memories for consumer market.
The first and very radical radiation hardening by design technique adopted for SkyFlash roadmap has been the redundancy of the bit. In standard non volatile memories each bit is stored in one cell only; in SkyFlash the bit is stored in two memory cells located in different part of the array.
This radical solution is supported by two reasons. The first is that in standard device the cell content is discriminated by a reference cell which is in common for the whole array; this reference cell, carefully programmed once manufactured the devices, represents a bottleneck since it is prone to radiation exactly like all the other cells. The degradation of a reference cell is an event that can damage not only one bit but all the device. Moreover the reference cell is programmed in an intermediate state: if the bit “0” is a memory cell completely empty of electrons and the bit “1” is a cell completely full of electrons on the other hand the reference cell must filled partially (half full) in order to be able to provide a discrimination. The distance of the reference cell to cells programmed with “0” or “1” is called Margin Window and it is one of the most important parameter to be considered in terms of device performance. The reference cell is a relevant threat for hostile environments such as space.
The second reason for choosing the storage of a single bit in two cells is based on the assumption that twin cells can be considered more safe and since the placement of the storage elements are in different parts of the array a single impinging of a charged particle cannot affect both.
The drawback of this approach is clear: the memory array must be doubled but this is something that is also done when using Error Correction Code (ECC) based system in standard device.
SkyFlash Roadmap has not considered ECC systems because this is usually done outside the chip at board level.
The double cell approach guarantees a very wide Margin Window and dramatically reduce the probability of bit loss but have driven to a very specific internal architecture where, first of all, programming and erasing must be carried on in a very different way respect to standard consumer non volatile memories.
From the architectural point of view it comes out that SkyFlash has proposed a device very similar to SRAMs when it is in read mode and more close to standard Flash when it is in program/erase mode. This approach has been further pushed ahead providing in read mode an asynchronous approach and treating program/erase mode synchronously. The main difference is the clock signal. In an asynchronous device there is no clock nor phase generation inside the chip and considering that clock trees are one of the most relevant place where single event upsets take place the complete removal of clocks and phase guarantee a safer condition against charge particles. In synchronous device, in this case necessary to feed charge pumps and simple state machines for programming and erasing, clock signal are propagated inside the chip but only when these operation are required.
It must be underlined that program/erase mode is less frequent than read mode (the major part of the operations are focused on reading) and this is the reason why SkyFlash Roadmap has considered the asynchronous approach during reading: to prolong the lifecycle and keep the device in a safer condition for the major part of the time.
In SkyFlash read and program/erase mode are considered two different worlds. The separation between synchronous and asynchronous modes leads to different and separated circuitry. In read mode a decoding is used to access the array from the drain side of the cells while in program/erase mode a different decoding system gain access to array passing through the source side of the cell. It is like gaining access to the same road from two different directions using two different cars. It is clear that programming circuits are more prone to radiation because of clocks and high voltages used for injecting charge in the floating trap celle but it is also true they are used less in the entire lifecycle of the device. On the other hand reading circuitry is more used indeed but since there are not clock trees and voltage are kept low (max 3.3V) degradation is mitigated.
SkyFlash Roadmap has considered also possible solutions in terms of circuits and physical layout of the chip. One of the weakest part of a non volatile memory is certainly represented by bandgap references (used to obtain specific voltage value in particular during programming and erasing) and charge pumps (used to boost up voltages during programming and erasing). In standard consumer devices charge pumps are usually burned by latch-up (Single Event Latch-up) and bandgap references provide wrong values due to total dose exposure.
In SkyFlash these parts has been designed to be rad-hard and they have been tested both outside as stand alone chips and inside SkyFlash prototypes confirming not only it is possible to provide resistance against radiation but also embedding into future rad-hard non volatile memories.
According to this approach several prototypes have been designed and integrated:
RC27FSKY1 Basic architecture prototype Silicon Available (July 2012)
RC27F1024SKY1 1Mbit OTP with ext. HV Silicon Available (December 2012)
RC27F1024SKY2 1Mbit OTP with charge pumps Silicon Available (April 2013)
RC27F1024SKY3 1Mbit OTP with charge pumps Silicon Available (May 2013)
RC27F1024SKY4 1Mbit OTP with band-gap Silicon Available (July 2013)
RC27F1024SKY5 1Mbit OTP Final Silicon Available (October 2013)
RC28F1024SKY1 1Mbit NVM with ext. HV Silicon Available (February 2014)
RC27F1024SKY6 1Mbit OTP Final release 2 Silicon Expected (March 2014)
RC27FSKY1 represents the very first device where the main issue has been to demonstrate the possibility to integrate a memory cell based on S-Flash with a rad-hard periphery. S-Flash cell has the great advantage to use one additional mask only during manufacturing process and it envisages the use of 3.3V transistors only because 1.8V masks are used for the array. This trick guarantees a flow very similar to a standard CMOS flow with both 1.8V and 3.3V thus leading to a yield typical of a standard CMOS process. RC27FSKY1 has been a manufacturing test (reading operation has been very simple) but it demonstrated it was possible to integrate rad-hard transistors with edgeless shape with S-Flash large matrices.
RC27F1024SKY1 is the first prototype heavily focused on read mode operations. It has not internal charge pumps nor bandgap references and high voltage for programming is provided by a specific external pin. Moreover it has not the possibility to erase programmed cell thus leading to a One Time Programmable (OTP) device. The simple structure and the robustness provided by the complete exclusion of programming parts led to a device more similar to a SRAM than to an NVM. RC27F1024SKY1 has been deeply irradiated demonstrating a resistance up to 300krad, result in line on what expected in the SkyFlash Roadmap.
RC27F1024SKY2 represents a step ahead in the integration of a rad-hard NVM. This device embeds charge pumps only for programming thus leading to an OTP very similar to the previous one but not requiring the external pin for high voltage since they are generated internally. RC27F1024SKY2 represents a quantum leap in rad-hard NVM scenario because it has been demonstrated by irradiating with high energy xenon ions that charge pumps are stable and not prone to latch-up together with the whole device.
RC27F1024SKY3 represents a further step ahead in the management of the memory array. From the architectural point of view it is similar to RC27F1024SKY2 but for programming and erasing issues a set of reference cells (not programmed but fed by using bandgap references) has been implemented in order to have a more efficient programming and erasing methodology. Even of more complex the approach guarantees a more efficient approach in moving the threshold voltage of cells to be programmed and avoid an over-programming which can lead an higher stress if silicon dioxide during hot channel injection.
RC27F1024SKY4 is a further step ahead of RC271024FSKY3 and embeds all bandgap references. In this device a preliminary erasing capacity is provided even if not optimized.
RC27F1024SKY5 is the final device complete of programming and erasing and RC27F1024SKY6 is the bug cleaned release of RC27F1024SKY5.
Behind RC27F family it is worth to mention RC28F1024SKY1 coming from the project of RC27F1024SKY4 and were the memory array has replaced with a difference cell (CEONOS cell). This approach has been particularly effective because it has been demonstrated that keeping the same periphery it was possible to change cell thus opening to very interesting scenarios for possible future commercial devices. As well known to those skilled in the art the replacemente of a memory cell is not an easy task but thanks to the very solid and general purpose periphery it has been possible to change an S-Flash cell (base on a process with one additional mask only) with a CEONOS cell (based on a standard NVM flow for commercial applications).
The large number of prototypes realized could not be tested extensively because of lack of time and of course for the limited number of hours of beam time allocated in the project. This is the reason why only some prototypes have been irradiated leaving the others available for future tests once finished SkyFlash Project. In fact, according to the Description of Work (DoW), the goal was to define a roadmap focusing on design and test have been included as part of the design. In the overall economy of the project 75% of the workload has been on design and 25% on testing but as a matter of fact parts are available for future actions and at disposals for those partners who intend to continue the research.
SkyFlash Project has completed its mission completing all tasks envisaged in the DoW. The roadmap is complete and at disposal thanks to the relevant number of deliverables and the high number of prototypes (each one having its peculiarity) provides an overview for future rad-hard component (also not strictly non volatile memories). SkyFlash was intended and really it is a technological platform with many useful information for further and more targeted device in the field of non volatile memories for space applications.
Potential Impact:
SkyFlash Project, according to its mission, has been focused on the main achievement envisaged by the European Union and the European Space Agency: the technology independence in the field of semiconductor components in general and NVMs in particular. In this description it will be mentioned ITAR rules and Dual Use rules (Wassermann Agreement) and how the efforts of SkyFlash have maintained the approach to provide a basic technology (enabling platform) to be used by the overall space community without any restriction according to the Technology Independence assumption.
ITAR and Wassermann
During the Cold War started after the end of the Word War II the US Department of Defense issued a set of rules to be used to restrict the circulation of specific technologies from the US to the USSR. These were years were the main focus was on nuclear weapons and all technologies were evaluated under the point of view of building weapons (uranium and plutonium enrichment, engines for rockets, etc…) but all kinds of technologies were indeed sensible to be used to obtain a strategic advantage against the counterpart. International Traffic Arm Regulation (ITAR) is a set of rules having as a main purpose to evaluate if a specific technology can be used for military applications or if it is and will be only a civilian technology. Recognizing such aspects may be difficult and as a matter of fact potentially the major part of new technologies may be seen under the point of view of “weapon building”. Once recognized to be strategic ITAR rules restrict their use for every kind of application and admit the free circulation only inside the US. ITAR rules do not forbid the circulation outside the US but traceability must be guaranteed by the end user(s).
In the field of semiconductor technologies ITAR rules found a very wide arena were to operate. As well known to those skilled in the art semiconductors represented since the beginning not a single monolithic technology but a set of very different technologies spreading from electronics (circuit design) to chemistry (manufacturing process), from information technologies (firmware and software) to new materials (silicon, oxides deposition, nitrides, passivating glasses, etc…).
The chain-flow for a chip manufacturing can be very long and it does not matter if the final application is a die for a mobile phone or a memory for a USB stick; one of the rings of this chain may have inside a technology potentially usable in weapons.
At the end of the ’90s ITAR rules seemed to be more relaxed but after the attack of September 11th a reinforcement of these rules took place. Again the approach was on the restriction of basic technologies but in the same time it was also a spring of collaborations in many fields including space. International Space Station (ISS) is one of the most important step toward an operative approach to a common technology to be used for the benefit of the whole mankind and it represents the de facto example of a place where all the flags are one flag only. When the mankind will travel to Mars (it is a matter of “when” not a matter of “if”) this will be done with an extended collaboration and all available efforts, technologies and commitment from parties coming from every angle of the world will be required.
During the FP7 MEGAHIT Conference (http://www.megahit-eu.org/) on December 2013 many discussions have been focused on the necessity to share technologies and efforts and indeed many countries were represented (US, Russian Federation, Korea, Japan, Europe). From a technical point of view the number of difficulties to take men on Mars is relevant but the most valuable aspect (appreciable also for those having a low skill in thrusters and power engines) has been the focus on technology sharing; it make no sense to restrict a technology that can be used for this important step of the mankind.
ITAR rules still exist but it is also true that they are trying to change their skin. ITAR technologies can be used by European companies (or from other countries) but there are still some problems in tracing information and end users.
In space the final application (e.g. a satellite) may be involved for several reasons and used by many parties: knowing everything from everybody may be an issue. This is the reason why a simplification process is on-going also from ITAR rules. Moreover if ITAR represent a problem from the end user point of view it is also an obstacle for US manufacturers. In the field of semiconductor components is well know how Aeroflex has established a European company (Gaislier) in order to be able to sell components in Europe. Maxwell, another well known US manufacturer, has established Maxwell UK, an independent European company selling ITAR free components. If this is true for those who sell component the same approach is valid for silicon foundries. Peregrine Semiconductor has split in two parts: Peregrine on the US side and Silanna in Australia for the ITAR-free market. Tower Semiconductors, partner of SkyFlash project, is the ITAR-free part of TowerJazz Corporate where Jazz represents the US side of the company with independent manufacturing lines.
If the business model is trying to overtake these restrictions with a relevant effort (maintaining two different companies who must be completely independent is very expensive) on the other side the US Department of Defence is trying to smooth the situation.
ITAR is not the only one; in Europe there are rules for the non-proliferation under the Wassermann Agreement stating that some technologies may become Dual Use, meaning the same can be used for both civilian and military applications. Just to give an example a rad-hard component like a NVM tolerant to total dose over 500Krad is considered Dual Use and for this reason must be traced by competent institutions (in Italy the Ministry of Economic Development, in Israel the Ministry of Industry). The main difference between Wassermann and ITAR is that for the first it does not exist a strategic technology tout-court. A technology may become strategic (or Dual Use) if it exceed specific limits like the one mentioned before. If from the Wassermann point of view it is complex to define such limits (ITAR only recognize the strategic technology) on the other side for the owner (or the end user) of such technology the advantage is that it can be used with the condition to not overcome the established limits.
Radiation Hardening By Design, the main pillar of SkyFlash Project, takes the best from the Wasserman approach because, as a matter of fact, a RHBD component can be completely restricted under the ITAR point of view but from the Wasserman point of view it is restricted only if it exceeds specific limits. This is a quantum leap from the restriction rules point of view.
RHBD, as mentioned in the major part of SkyFlash deliverables and DoW, is a set of techniques and all these methods may be used in a very different way. By applying all annular transistors (NMOS and PMOS), using enhanced guard-rings everywhere and all the techniques described in the literature of SkyFlash it is indeed possible to overtake this value; but it is also possible to relax these rules and provide a device rad-hard enough for the mission (LEO, MEO, GEO) or rad-hard enough to not overtake Wasserman rules. This is a new concept of design based on efficiency, cost and rule observation and SkyFlash consortium is convinced it will be the new approach for future rad-hard component design.
Technology Independence
National and International rules are of course one the obstacles for a real technology independence but other perspectives must be included. A very tailored technology with high complexity where only few players (or only one) can apply changes can represent a restriction exactly like ITAR. In this case two aspects must be evaluated: on one side the technology itself can represent a bottleneck if the complexity inside is to high while on the other the presence of few players (or only one), even if private, may represent an obstacle.
Like persons technologies should be replaceable and like working team, where best characters are chosen more or less the same should be done for enabling technologies.
In the field of semiconductor components there are some assumptions that can be considered. A rad-hard component is usually the result of a silicon process flow (CMOS, SOI, SiGe, etc…) combined with a design flow (circuit design, layout design, firmware and software); the result is a die that must be bonded in a package and finally tested in order to have the green light to be used. Very tailored technologies may be risky because when specific processes are used it is possible that repeat-ability can become an issue. Rad Hard By Process (RHBP) is very keen to obsolescence because of low volume of devices manufactures. Indeed RHBP processes exist (e.g. American Semiconductor) but apart to be ITAR they are also restricted by their small niche of applications. As well known to those skilled in semiconductor manufacturing the higher is the number of manufactured lots the higher is the maturity obtained by the process itself. CMOS 180nm process, the one used in the overall life cycle of SkyFlash Project, represent a well consolidated and mature process. Twenty years ago it was the edge of the technology and now there are much more aggressive process (e.g. 45nm or 22nm) but in these twenty years many wafers by many foundries has been fabricated. Nowadays the yield is in the range of 99,5% and even if this is not an issue for rad-hard components which can of course be much more expensive than a commercial one nevertheless it shows that manufacturing line have the complete control of the process. This is another way to see what a component for space application looks for: repeat-ability; what is manufactured now can be reproduced with almost 100% probability of success. This is Technology Independence.
Since 180nm process is manufactured by many foundries it is also possible to move the design of the component. For sure a technology may be restricted by national rules but it is also possible that the foundry itself change its business or abandon the specific market because not considered strategic. The possibility to move the design from a 180nm platform to another 180nm platform, even if it requires some efforts, is one of the key point for a winning space components. Again, this is Technology Independence.
Manufacturing processes are not forever. This is a basic assumption that Space Community must consider. Nowadays CMOS 180nm is indeed the most suitable for a space component but the Moore Law is (still) running and the technology is moving into the deep submicron era. Silicon foundries are still interested to maintain manufacturing line alive and in good shape but the major part of the income is from consumer market and now this market is not represented by microprocessors, memories and other components sold in billion of parts but it is the market of low level applications such as cheap mobile phones, basic video games or custom applications from small and medium enterprise. Twenty years ago 180nm was terribly expensive and only Intel, AMD, Motorola could afford such technology; now they look at 22nm. But small and medium companies today can use 180nm and indeed they are doing.
This situation will not continue forever. One day also the low level market will move to a more scaled (90nm or less) technology and, consequently, silicon foundries will see also this income to be vanished and in that moment the space niche market will not be enough. This is a threat to Technology Independence.
Saying for how many years 180nm will be available it is rather hard. As a matter of fact there are manufacturing lines still delivering wafers under 250nm so at least other 10 years are reasonable to be expected but the space community must start consider a mid-long term situation with a new process and under these premises there are two options: 90nm or 65nm.
Nowadays CMOS 90nm process is starting to become an old technology (UMC itself is trying to push all its customers towards 65nm) but indeed it has a good level of maturity and this can benefit the space community. On the other hand there is the problem that many foundries has decided to skip this technological node and target directly to the next one represented by 65nm. Under this perspective the risk is to move rad-hard design (including IP cores, VHDL/Verilog codes and rad-hard libraries) to a process that will have a limited success in the low level market. If the low level market will stay on 90nm process (available by a reduced number of silicon foundries if compared to 180nm) for a shorter period the time window for space market can be very narrow forcing to move again to another node (65nm or less).
This is the hard decision to be taken today. CMOS 180nm is reliable for today and tomorrow space products but for the future it is possible that a direct jump to 65nm could be more safe than the one to 90nm.
It is clear that a more scaled technology has some advantages and some disadvantages. In the first one we can mention the resistance in terms of total dose. 90nm and 65nm may rely on thinner oxides and much more clean STI thanks to a more clean deposition removing impurities at the base of holes trapping. For LEO, MEO and GEO it is possible that a very limited number of edgeless transistors can be used with the great advantage to save area in the die. On the other hand the reduced lithography and the reduced junction capacitance at transistor terminals leads to a reduced critical charge in sensitive nodes of the device. Charged particles with lower energy may upset logic ports and memory elements more easily thus leading to increased sensitivity against SEUs, SETs, MBUs and more in general SEFIs. From the hard error perspective also in this case lower energies may be required to trigger a SEL or a SEGR (the last one in particular because of the reduced thickness of oxides) thus leading to enhanced guard rings (waste of area).
RHBD techniques are expected to be adapted in the case of a new technology node. SEE in particular will require on one hand a careful design of circuitry handling with SETs and on the other improved techniques for error correction are expected (with the disadvantage to waste area).
The roadmap defined and pursued in SkyFlash Project had taken into account these premises. Nowadays a 180nm CMOS process has been adopted but in the future a scaled technology is envisaged. Understanding the impact of techniques of radiation hardening by design means to enable and adapt them also in future technologies according to the tradeoff required by resistance against radiation and area consumption. If annular device will probably become the domain for deep space missions only on the other hand enhanced guard ring or new means of shielding will become the main issues for every reliable component (also for LEOs).
In 180nm ECC is not required or it can be lightly used. In more scaled technology ECC will be mandatory to recover the high sensitivity to SEUs in storage elements (SRAMs, Flip-Flops) opening the world of rad-hard on-chip ECCs.
All NVM prototypes developed in SkyFlash have been based on a very radical architectural approach: the use of two memory cells to store a single bit. This is not redundancy nor ECC. A traditional ECC should be based on a 1Mbit array storing data and a second 1Mbit array storing data able to correct the first array (deep Hamming Code) with the inclusion of a digital block intercepting errors and providing corrected bytes. In SkyFlash the bit itself has changed nature and there is no correction: the bit composed by twin cells is more reliable without any correction.
This radical RHBD approach has obviously impacted the overall architecture of the memory. In a conventional ECC approach the single memory block should be the same of a standard memory (same decoders, same sensing scheme, same programming and erasing) but this weakness should be maintained by its intrinsic nature of a device born to work in a standard environment without radiation. On the other hand SkyFlash prototypes have been redesigned from scratch. The physical separation inside the die of the twin cells storing the single bit is a precise decision to avoid that the same ion strike may hit the single bit. The complete removal of reference cells traditionally used in standard NVM has been a precise decision to avoid weak elements which can suffer the degradation from total dose exposure. The decision to use a clock to program and erase a memory and to switch off the same during read mode making the same memory more similar to an asynchronous SRAM is part of a specific RHBD strategy has been done in order to obtain a more safe design against both soft and hard errors.
SkyFlash roadmap has defined not only tricks and methods to avoid or mitigate radiation effects but also new means of architecture and floor-planning. Several general assumption on how to realize a rad-hard device are indeed typical of memory design but they can easily moved to a more general mixed signal IC. Moreover all these assumption are independent from the technology node. In SkyFlash it has been on CMOS 180nm but the same approach and the general vision may be moved to 90nm or 65nm. Again, this is Technology Independence.
During the final meeting on February 28th 2014 and in deliverable D.1.7 has been reported a slide shown hereinafter summarizing the obtained achievements and defining future perspectives.
SkyFlash has represented an effort to a roadmap showing how a rad-hard memory can move through several available technologies. Today it is CMOS 180nm process with charge trap memory cells based on nitride but tomorrow it can be a more scaled technology (90nm or 65nm) with different memory cells (RRAM, PCM, MTJ). The strong methodological approach followed by SkyFlash has pursued the main pillar of Technology Independence such as strongly asked by the European Union and the European Space Agency.
Conclusion
SkyFlash Project has been concluded on time according to roadmap defined in the DoW. These 30 months has taken the knowledge of the Consortium in the field of NVM to a new level of awareness and many lessons have been learnt.
SkyFlash has been and will be a relevant platform for future endeavors in the same field by using new technologies and manufacturing process.
List of Websites:
http://www.skyflash.eu/
Dr. Cristiano Calligaro, RedCat Devices srl, via Valsolda 21, 20142 MILANO (ITALY)
SkyFlash has been focused on the development of a strong rad-hard by design (RHBD) methodology for non volatile semiconductor memories to be used in space applications taking the best from standard CMOS (Complementary Metal-Oxide Semiconductor field effect transistors) submicron (180nm) silicon processes. The main ideas at the base of the project are the following: 1) development of rad-hard integrated silicon devices acting on the design more than on fabrication process; 2) application of non volatile memory technology (floating gate/floating trap cells) in space applications.
A key feature of integrated circuits destined to be used for space applications is that of radiation tolerance. Beyond the atmosphere (meaning in electronic equipment for satellites, probes or more in general spacecrafts) many particles (electrons, protons, high energy ions) collide with silicon devices releasing energy and possibly disrupt operations. There are two main effects of radiations on silicon devices: 1) long term effects (TID, Total Ionizing Dose); 2) short term and randomic effects (SEE, Single Event Effects).
Non volatile semiconductor memories in space market have been faced with old anti-fuse technologies till now; this means that media can be written (or burned) before the mission and only read during later on. This kind of device is called OTP (One Time Programmable) memory and is typically used for star maps or boot software storage and is the only one actually chosen by space market.
The real breakthrough for the introduction of programmable and erasable non volatile memories is the introduction of floating gate (or floating trap) memory cells.
Many problems arise on this well known technology since the ’60s but never used for rad-environments. The first one is the retention of the bit: a floating gate cell stores electrons in a sandwich of poly-silicon (or silicon nitride for floating trap, also known as charge trap) surrounded by silicon dioxide thus leading to a variable threshold proportional to the amount of electrons trapped; the exposure of the cell to an amount of radiations can move, during time, the threshold itself so changing the bit. Moreover, in terms of single events, an high energy particle can collide with a floating gate and if the energy is sufficiently high it is possible that trapped electrons can gain energy enough to migrate outside their traps.
It is worth mentioning that even if these aspects has been studied the technology and the methodology adopted were commercial: no efforts were dedicated to design a non volatile device to be rad-hard.
A non-volatile memory has other aspects that could be crucial for rad-environment: the circuitry for programming (state machines and program & verify algorithms), circuits for high voltage generation (typically a floating gate/trap cell need, to be written, a voltage more than double to power supply), circuits and algorithms for erase operations.
All blocks not directly related to non volatile memory cells and their organization in one or more arrays are generally called “periphery”. These blocks includes decoders, row and columns final stages, sense amplifiers for reading, buffers and high voltages part devoted to program end erase memory cells. If on side the memory cells must be stable in their retention job against radiations on the other the periphery must guarantee the right functioning avoiding degradation under TID and soft errors (and hard errors as well) when single events occur (SEE).
Since SkyFlash uses a standard CMOS 180nm process no dedicated processes are envisaged and for this reason all radiation hardening approaches are on focused on design only (Radiation Hardening By Design, RHBD).
RHBD methodologies previously developed by RedCat Devices in SRAMs has been extensively used in SkyFlash in combination with rad-hard charge pumps, high voltage distributions, band-gap references and basic logic to implement program and erase algorithm.
The final target has been the development of a 1Mbit reprogrammable prototype memory, single power supply, complete of all basic blocks required by all NVMs.
Project Context and Objectives:
The context addressed for SkyFlash project has been SPA.2011.2.2-02 Space critical technology and in particular ASICs (Support to existing 0.18 um technologies) for space application. This topics, as part of FP7 Space, has been faced also by ESA (European Space Agency) in several tenders tenders in the past (09.1QC.08 Reliability testing of commercial available flash memories (follow on from: radiation assessment of commercial flash); 09.1EP.02 Study of mitigation techniques/optimisation for analogue circuits in space radiation environment; 09.1QC.02 Radiation tolerant analogue/mixed signal technology survey and test vehicle design; 09.1QC.07 Technology assessment of dram and advanced memory products following in from radiation test and benchmark of commercial products against space requirements). The integrated circuits for space application scenario is quite peculiar; since silicon processes are large corporate prerogative it’s clear that these companies serve a very large market. All technological and scientific efforts are pushed to applications satisfying a consumer market, not a niche one. In this number we can include mobile phones, personal and notebook computers and so on. The benefits coming from a strong research in silicon processes for size reduction (transistors channel length) and enhancing performance (clock speed) give rise to more compact and more power final product (more and more small mobile phones with performance so high to include software applications for internet networking or e-mail management).
It’s clear that these scientific and technological efforts, following the well known Moore Law, are tracing a precise track in which there is only the consumer market.
Space electronics is a niche market but has also high-level requirements which basically are not satisfied by standard consumer electronics. These requirements, as explained above, are first of all the resistance to radiation but mechanical resistance (during launch) and thermal resistance too. Large silicon foundries, due to low volumes required by space market, are not appealed by these requirements and the result is a base technology which is not suited for space. The result is a technology lack.
Another aspect to be underlined is connected to the availability of some dedicated technology developed for military industry. In USA some silicon foundries (e.g. American Semiconductor) has developed silicon processes with a certain resistance to radiation and are involved in device design for military applications. The main problem related to such realities is that these players can only work for militaries and cannot provide either their components and their technology outside US: that’s called ITAR (International Traffic in Arms Regulations) which is a set of rules that control the export and import of defence-related articles and services. ITAR was activated during Cold War and reinforced more recently after September 11th 2001 and restricts all base technologies which can be used for weapon building including fighters or soldier equipment. The resistance to radiations is obviously considered and silicon processes for integrated circuits realised for military market fall under ITAR restrictions.
Space market and high energy physics market pay the drawback of this approach and the result, from silicon processes point of view, is that on one side basically there is a shortage of rad-hard technology and, on the other side, when a technology is developed it can fall under ITAR restrictions so becoming unavailable as well.
European Space Agency (ESA) and all European large scale integrators find difficulties in providing components and technologies for their production and this is the reason why they are pushing on ITAR FREE technologies, meaning a set of base and critical technologies which could be freely used by ESA members and their providers and integrators. ESA strongly aims to a base technology internally (meaning in Europe) developed which could not be included in ITAR or other restrictions.
Project Results:
SkyFlash project has been focused on the development of non volatile memories for space applications. It is worth to underline that the main issue is related to the single memory cell to be used to store the bit. Volatile memories, in fact, do not use any specific media but a very simple ensemble of standard transistors connected in a way to obtain a bistable circuit or, in other word, an elementary element to store the bit in its form of “0” or “1”. Without power supply the bistable element cannot store the data any more and the result is that data is lost: this is the volatile element. Non volatility is obtained by using more complex phenomena able to provide a state stable also without power supply thus moving the focus from the traditional electronic (or microelectronic) approach to the domain of physics.
Standard consumer non volatile memories (such as those used in USB sticks or as computer solid state hard drives) basically use so called floating gate or floating trap cells. The approach is very simple and is based on the insulation of poly-silicon (or nitride) by using silicon dioxide.
Silicon dioxide represent an almost perfect insulator and this behaviour guarantees the impossibility of any movement for electrons and holes (the counter part of electrons) even if it is better to say that movement can be obtained only at certain conditions and certain energies. A poly-silicon (or media) embedded in a silicon dioxide block represents a region where electrons can freely move inside such as a free chamber. The presence of trapped electrons in the chamber or their absence determines the bit status (poly-silicon or nitride filled of electrons represent “1”, the absence of electrons represent “0”) and this status may be detected thanks to capacitive coupling coming from the standard three terminals of a transistor. When power supply is removed electrons remain trapped in poly-silicon or nitride media and their energy is not enough to override the barrier represented by the surrounding silicon dioxide. They are like prisoners that cannot gain enough speed to escape from the jail and silicon dioxide are concrete walls.
Injecting electrons onto poly-silicon or nitride is not an easy task and taking them out is difficult as well. There are basically two methods based on two physical phenomena: the first is called Hot Electron Injection or, more commonly, Channel Hot Injection (CHE) and is based on a cascade of electrons flowing into the channel of a standard transistor. This cascade is provided by high voltages applied at the terminal of the transistor and has the target not to make flowing an high number of electrons but to give them enough energy to jump the potential barrier of the silicon dioxide and reach the buried floating gate (or floating trap); not all electrons will gain enough energy but this condition guarantees that some “lucky” electrons will be able to be injected. Channel injection is a quite rude to method to store electrons but has the great advantage to be easy to be triggered. On the other side the main drawback a the stress induced to silicon dioxide (prisoner-electrons can go in and go out but concrete silicon-dioxide walls are damaged time after time).
The second physical phenomenon used to store electrons is the Quantum Mechanical Tunnelling and it can be divided in two phenomena according to the thickness of the silicon dioxide. If the dioxide is thin enough an electron (at specific high voltage conditions) can be injected directly onto the floating gate or floating trap completely skipping the oxide layer; in this case we talk about Direct Tunnelling. With thicker dioxides the same operation can be obtained at similar conditions but electrons tunnel into the conduction band of the silicon dioxide where they can flow into the cathode represented the floating gate or floating trap; in this case we talk about Fowler-Nordheim Tunnelling. With Direct Tunnelling electrons are injected directly onto the chamber; with Fowler-Nordheim Tunnelling electrons are injected on the door of the chamber and then collected inside. Tunnelling is a method less rude than hot carriers injection thus leading to a lower dioxide degradation but from the manufacturing point of view it requires more sophisticated technologies lacking of reliability (in particular if the considered environment is hostile).
Floating gate (based on poly-silicon) or floating trap (based on nitride) are not the only media used for non volatile memories. Emerging technologies involving phase change, resistive or magnetic material are starting to be considered both for consumer markets and special markets such as space.
Phase Change Memories (PCM), also known as Chalcogenide Memories, are based on new material able to change their state from amorphous to crystalline under specific conditions. By heating these layers it is possible to obtain an hysteresis cycle that, at the end, provide a difference resistance where electron can flow. High resistance leads to a “1” and low resistance leads to a “0” (or viceversa according to the architecture used in the final application) and when power supply is over the phase of the material is not changed.
Resistive memories use the same approach but material are different; in this case layer containing hafnium oxide create a set of connection between different layer enhancing or reducing the overall resistance according to their number. Like PCM everything is played with higher or lower current but in this case it is a matter of nano-connections taking in communication different electrodes.
Magnetic memories are based on Tunnel Magneto-Resistance (TMR) which is a magneto-resistive effect that occurs in magnetic tunnel junctions (MTJs). This effect occurs in particular in ultra-thin (few nanometers) multi-layers of magnetic materials separated by a metallic (GMR, Giant Magneto-Resistance) or insulating (TMR) film. In the case of TMR, if the insulating layer is thin enough electrons can tunnel from one ferromagnet to the other and due to the fact that this process is forbidden in classical physics the tunnel magneto-resistance is strictly considered a quantum-mechanical phenomenon.
The above mentioned emerging technologies pay the drawback of the low maturity respect to floating gate and floating trap memories which are running since the ’60 and maturity, together with reliability, is one of the key assets for space electronics.
SkyFlash Project has been focused, according to technological independence request coming from the call, on the development of a roadmap concerning non volatile memories starting from the most reliable option actually available and represented by nitride memories.
Nitride and poly-silicon memories are very similar in the basic principles and also in the manufacturing flow but the first is an insulator while the second is a conductive material. Electrons injected in a poly-silicon media can still move inside while in nitride they are frozen in a specific location. In the floating gate it is not possible to determine the position of the charges, in nitride they are located in a cloud exactly in the position where they have been injected and according to their status the probability to be extracted by the media is lower in consideration of the fact they have less probability to gain enough energy to escape.
For the above mentioned reasons SkyFlash has considered nitride devices that, specifically, has been S-Flash (Sidewalls Flash) cells and CEONOS (Cost Efficient Oxide-Nitride-Oxide Silicon) both coming from a background properties of Tower Semiconductor. It is clear that the approach followed by SkyFlash is inclusive and not exclusive so the major part of the solutions can be moved also to floating gate memory cells or different kind of cells including PCM, resistive and magnetic.
The SkyFlash Roadmap has been based on Radiation Hardening By Design which is the main pillar in combination with a mature and reliable technology such as a standard 180nm CMOS process and a relevant experience coming from the major part of the partners in the field of rad-hard SRAMs.
The background expertise has played an important role also in the field of testing under irradiation. As well known to those skilled in the art microelectronic device design is very closely related with testing and when the final device is expected to be rad-hard this relation becomes stronger. Testing a rad-hard component is not an easy task; first of all tests must be done on Earth and the same conditions must be reliably reproduced. Moreover, in particular for total dose irradiation, tests must be accelerated because the effects in space spreading in a time line of years must be reduced to days in Earth. So, total dose, two aspects must be considered: 1) reproduction of space environment on Earth; 2) accelerated test to avoid expensive and time consuming procedures. Keeping these aspects under control means having in the consortium the necessary expertise and this is the reason why SkyFlash Consortium, even if the project has been heavily focused on the design, has decided to include partners devoted to total dose irradiation and not making use of subcontractors. The commitment on testing has been one of the pillar from the management point of view.
Single event testing may be considered in some ways more “reproducible” on Earth compared to total dose. Charged particles may be the same as in space and considering the fact these events are stochastic all issues related to accelerated tests are not an issue. On the other hand the equipment is more complex and difficult to be taken under control. If in total dose Gamma Ray and X-Ray chambers irradiation is delivered in conditions to be taken strictly under control from the point of view of the dosimetry (not to high because the test may be not in line on what happen in space and not to low to avoid long test) on the other hand with heavy ions and protons linear accelerator must be used and the complexity of such machines is relevant. Moreover the beam (heavy ions with xenon, nitrogen, or other) must be carefully prepared in terms of fluence, dimension of the window and, last but not least, Bragg Peak release. Since the effect is the release of energy it is important the maximum of energy coming from charged particles is not release in the back end of line (BEOL) of the chip were metals only interconnect transistors but in front end of line (FEOL) or, in other words, were transistors are manufactured and were the beam can really give a soft error or an hard error to the chip. Release the peak of energy in the exact position in depth of the chip is not an easy task and, again, this is the reason why SkyFlash consortium has decided to include as a partner, instead as a subcontractors, the required actors. For protons the same consideration are valid and SkyFlash Consortium has indeed produced a significant advance in testing also in the field of cross relations between total dose and single event effects enlarging the roadmap also in the field of testing.
As deeply discussed during the final meeting at the presence of the project officer and the technical reviewer, SkyFlash project has tested several parts under protons considering on one hand the possibility of soft errors (upsets) but on the other hand, thanks to the nuclear effect coming from the collision of protons producing secondary irradiation, also the degradation in terms of total dose. In short words SkyFlash has evaluated not only soft errors tout-court but soft errors when the component is fresh and when the it has been degraded by total dose. This is something ESA is carefully considering as well stated in ITT 7751 (Total Ionizing Dose Influence on the single event effect sensitivity of active EEE components) and this tells that SkyFlash has in some way anticipated a general need coming from the space community.
SkyFlash roadmap for the development of rad-hard non volatile memories has considered several aspects of whole. From the architectural point of view many assumptions came from rad-hard SRAMs but, as a matter of fact, the memory array is quite different thus leading to different effects when the device is irradiated. In non volatile memory cells bit upsets coming from the impinging of a charged particle is not an issue because the bit is not stored in a bistable element but in a single transistor having one state only. This does not mean that in a non volatile memory upsets cannot occur but that they are more probable outside the array in the periphery or in the output buffers taking the data outside the chip. This simple statement led to a very peculiar architectural approach relevantly different from the one adopted by standard non volatile memories for consumer market.
The first and very radical radiation hardening by design technique adopted for SkyFlash roadmap has been the redundancy of the bit. In standard non volatile memories each bit is stored in one cell only; in SkyFlash the bit is stored in two memory cells located in different part of the array.
This radical solution is supported by two reasons. The first is that in standard device the cell content is discriminated by a reference cell which is in common for the whole array; this reference cell, carefully programmed once manufactured the devices, represents a bottleneck since it is prone to radiation exactly like all the other cells. The degradation of a reference cell is an event that can damage not only one bit but all the device. Moreover the reference cell is programmed in an intermediate state: if the bit “0” is a memory cell completely empty of electrons and the bit “1” is a cell completely full of electrons on the other hand the reference cell must filled partially (half full) in order to be able to provide a discrimination. The distance of the reference cell to cells programmed with “0” or “1” is called Margin Window and it is one of the most important parameter to be considered in terms of device performance. The reference cell is a relevant threat for hostile environments such as space.
The second reason for choosing the storage of a single bit in two cells is based on the assumption that twin cells can be considered more safe and since the placement of the storage elements are in different parts of the array a single impinging of a charged particle cannot affect both.
The drawback of this approach is clear: the memory array must be doubled but this is something that is also done when using Error Correction Code (ECC) based system in standard device.
SkyFlash Roadmap has not considered ECC systems because this is usually done outside the chip at board level.
The double cell approach guarantees a very wide Margin Window and dramatically reduce the probability of bit loss but have driven to a very specific internal architecture where, first of all, programming and erasing must be carried on in a very different way respect to standard consumer non volatile memories.
From the architectural point of view it comes out that SkyFlash has proposed a device very similar to SRAMs when it is in read mode and more close to standard Flash when it is in program/erase mode. This approach has been further pushed ahead providing in read mode an asynchronous approach and treating program/erase mode synchronously. The main difference is the clock signal. In an asynchronous device there is no clock nor phase generation inside the chip and considering that clock trees are one of the most relevant place where single event upsets take place the complete removal of clocks and phase guarantee a safer condition against charge particles. In synchronous device, in this case necessary to feed charge pumps and simple state machines for programming and erasing, clock signal are propagated inside the chip but only when these operation are required.
It must be underlined that program/erase mode is less frequent than read mode (the major part of the operations are focused on reading) and this is the reason why SkyFlash Roadmap has considered the asynchronous approach during reading: to prolong the lifecycle and keep the device in a safer condition for the major part of the time.
In SkyFlash read and program/erase mode are considered two different worlds. The separation between synchronous and asynchronous modes leads to different and separated circuitry. In read mode a decoding is used to access the array from the drain side of the cells while in program/erase mode a different decoding system gain access to array passing through the source side of the cell. It is like gaining access to the same road from two different directions using two different cars. It is clear that programming circuits are more prone to radiation because of clocks and high voltages used for injecting charge in the floating trap celle but it is also true they are used less in the entire lifecycle of the device. On the other hand reading circuitry is more used indeed but since there are not clock trees and voltage are kept low (max 3.3V) degradation is mitigated.
SkyFlash Roadmap has considered also possible solutions in terms of circuits and physical layout of the chip. One of the weakest part of a non volatile memory is certainly represented by bandgap references (used to obtain specific voltage value in particular during programming and erasing) and charge pumps (used to boost up voltages during programming and erasing). In standard consumer devices charge pumps are usually burned by latch-up (Single Event Latch-up) and bandgap references provide wrong values due to total dose exposure.
In SkyFlash these parts has been designed to be rad-hard and they have been tested both outside as stand alone chips and inside SkyFlash prototypes confirming not only it is possible to provide resistance against radiation but also embedding into future rad-hard non volatile memories.
According to this approach several prototypes have been designed and integrated:
RC27FSKY1 Basic architecture prototype Silicon Available (July 2012)
RC27F1024SKY1 1Mbit OTP with ext. HV Silicon Available (December 2012)
RC27F1024SKY2 1Mbit OTP with charge pumps Silicon Available (April 2013)
RC27F1024SKY3 1Mbit OTP with charge pumps Silicon Available (May 2013)
RC27F1024SKY4 1Mbit OTP with band-gap Silicon Available (July 2013)
RC27F1024SKY5 1Mbit OTP Final Silicon Available (October 2013)
RC28F1024SKY1 1Mbit NVM with ext. HV Silicon Available (February 2014)
RC27F1024SKY6 1Mbit OTP Final release 2 Silicon Expected (March 2014)
RC27FSKY1 represents the very first device where the main issue has been to demonstrate the possibility to integrate a memory cell based on S-Flash with a rad-hard periphery. S-Flash cell has the great advantage to use one additional mask only during manufacturing process and it envisages the use of 3.3V transistors only because 1.8V masks are used for the array. This trick guarantees a flow very similar to a standard CMOS flow with both 1.8V and 3.3V thus leading to a yield typical of a standard CMOS process. RC27FSKY1 has been a manufacturing test (reading operation has been very simple) but it demonstrated it was possible to integrate rad-hard transistors with edgeless shape with S-Flash large matrices.
RC27F1024SKY1 is the first prototype heavily focused on read mode operations. It has not internal charge pumps nor bandgap references and high voltage for programming is provided by a specific external pin. Moreover it has not the possibility to erase programmed cell thus leading to a One Time Programmable (OTP) device. The simple structure and the robustness provided by the complete exclusion of programming parts led to a device more similar to a SRAM than to an NVM. RC27F1024SKY1 has been deeply irradiated demonstrating a resistance up to 300krad, result in line on what expected in the SkyFlash Roadmap.
RC27F1024SKY2 represents a step ahead in the integration of a rad-hard NVM. This device embeds charge pumps only for programming thus leading to an OTP very similar to the previous one but not requiring the external pin for high voltage since they are generated internally. RC27F1024SKY2 represents a quantum leap in rad-hard NVM scenario because it has been demonstrated by irradiating with high energy xenon ions that charge pumps are stable and not prone to latch-up together with the whole device.
RC27F1024SKY3 represents a further step ahead in the management of the memory array. From the architectural point of view it is similar to RC27F1024SKY2 but for programming and erasing issues a set of reference cells (not programmed but fed by using bandgap references) has been implemented in order to have a more efficient programming and erasing methodology. Even of more complex the approach guarantees a more efficient approach in moving the threshold voltage of cells to be programmed and avoid an over-programming which can lead an higher stress if silicon dioxide during hot channel injection.
RC27F1024SKY4 is a further step ahead of RC271024FSKY3 and embeds all bandgap references. In this device a preliminary erasing capacity is provided even if not optimized.
RC27F1024SKY5 is the final device complete of programming and erasing and RC27F1024SKY6 is the bug cleaned release of RC27F1024SKY5.
Behind RC27F family it is worth to mention RC28F1024SKY1 coming from the project of RC27F1024SKY4 and were the memory array has replaced with a difference cell (CEONOS cell). This approach has been particularly effective because it has been demonstrated that keeping the same periphery it was possible to change cell thus opening to very interesting scenarios for possible future commercial devices. As well known to those skilled in the art the replacemente of a memory cell is not an easy task but thanks to the very solid and general purpose periphery it has been possible to change an S-Flash cell (base on a process with one additional mask only) with a CEONOS cell (based on a standard NVM flow for commercial applications).
The large number of prototypes realized could not be tested extensively because of lack of time and of course for the limited number of hours of beam time allocated in the project. This is the reason why only some prototypes have been irradiated leaving the others available for future tests once finished SkyFlash Project. In fact, according to the Description of Work (DoW), the goal was to define a roadmap focusing on design and test have been included as part of the design. In the overall economy of the project 75% of the workload has been on design and 25% on testing but as a matter of fact parts are available for future actions and at disposals for those partners who intend to continue the research.
SkyFlash Project has completed its mission completing all tasks envisaged in the DoW. The roadmap is complete and at disposal thanks to the relevant number of deliverables and the high number of prototypes (each one having its peculiarity) provides an overview for future rad-hard component (also not strictly non volatile memories). SkyFlash was intended and really it is a technological platform with many useful information for further and more targeted device in the field of non volatile memories for space applications.
Potential Impact:
SkyFlash Project, according to its mission, has been focused on the main achievement envisaged by the European Union and the European Space Agency: the technology independence in the field of semiconductor components in general and NVMs in particular. In this description it will be mentioned ITAR rules and Dual Use rules (Wassermann Agreement) and how the efforts of SkyFlash have maintained the approach to provide a basic technology (enabling platform) to be used by the overall space community without any restriction according to the Technology Independence assumption.
ITAR and Wassermann
During the Cold War started after the end of the Word War II the US Department of Defense issued a set of rules to be used to restrict the circulation of specific technologies from the US to the USSR. These were years were the main focus was on nuclear weapons and all technologies were evaluated under the point of view of building weapons (uranium and plutonium enrichment, engines for rockets, etc…) but all kinds of technologies were indeed sensible to be used to obtain a strategic advantage against the counterpart. International Traffic Arm Regulation (ITAR) is a set of rules having as a main purpose to evaluate if a specific technology can be used for military applications or if it is and will be only a civilian technology. Recognizing such aspects may be difficult and as a matter of fact potentially the major part of new technologies may be seen under the point of view of “weapon building”. Once recognized to be strategic ITAR rules restrict their use for every kind of application and admit the free circulation only inside the US. ITAR rules do not forbid the circulation outside the US but traceability must be guaranteed by the end user(s).
In the field of semiconductor technologies ITAR rules found a very wide arena were to operate. As well known to those skilled in the art semiconductors represented since the beginning not a single monolithic technology but a set of very different technologies spreading from electronics (circuit design) to chemistry (manufacturing process), from information technologies (firmware and software) to new materials (silicon, oxides deposition, nitrides, passivating glasses, etc…).
The chain-flow for a chip manufacturing can be very long and it does not matter if the final application is a die for a mobile phone or a memory for a USB stick; one of the rings of this chain may have inside a technology potentially usable in weapons.
At the end of the ’90s ITAR rules seemed to be more relaxed but after the attack of September 11th a reinforcement of these rules took place. Again the approach was on the restriction of basic technologies but in the same time it was also a spring of collaborations in many fields including space. International Space Station (ISS) is one of the most important step toward an operative approach to a common technology to be used for the benefit of the whole mankind and it represents the de facto example of a place where all the flags are one flag only. When the mankind will travel to Mars (it is a matter of “when” not a matter of “if”) this will be done with an extended collaboration and all available efforts, technologies and commitment from parties coming from every angle of the world will be required.
During the FP7 MEGAHIT Conference (http://www.megahit-eu.org/) on December 2013 many discussions have been focused on the necessity to share technologies and efforts and indeed many countries were represented (US, Russian Federation, Korea, Japan, Europe). From a technical point of view the number of difficulties to take men on Mars is relevant but the most valuable aspect (appreciable also for those having a low skill in thrusters and power engines) has been the focus on technology sharing; it make no sense to restrict a technology that can be used for this important step of the mankind.
ITAR rules still exist but it is also true that they are trying to change their skin. ITAR technologies can be used by European companies (or from other countries) but there are still some problems in tracing information and end users.
In space the final application (e.g. a satellite) may be involved for several reasons and used by many parties: knowing everything from everybody may be an issue. This is the reason why a simplification process is on-going also from ITAR rules. Moreover if ITAR represent a problem from the end user point of view it is also an obstacle for US manufacturers. In the field of semiconductor components is well know how Aeroflex has established a European company (Gaislier) in order to be able to sell components in Europe. Maxwell, another well known US manufacturer, has established Maxwell UK, an independent European company selling ITAR free components. If this is true for those who sell component the same approach is valid for silicon foundries. Peregrine Semiconductor has split in two parts: Peregrine on the US side and Silanna in Australia for the ITAR-free market. Tower Semiconductors, partner of SkyFlash project, is the ITAR-free part of TowerJazz Corporate where Jazz represents the US side of the company with independent manufacturing lines.
If the business model is trying to overtake these restrictions with a relevant effort (maintaining two different companies who must be completely independent is very expensive) on the other side the US Department of Defence is trying to smooth the situation.
ITAR is not the only one; in Europe there are rules for the non-proliferation under the Wassermann Agreement stating that some technologies may become Dual Use, meaning the same can be used for both civilian and military applications. Just to give an example a rad-hard component like a NVM tolerant to total dose over 500Krad is considered Dual Use and for this reason must be traced by competent institutions (in Italy the Ministry of Economic Development, in Israel the Ministry of Industry). The main difference between Wassermann and ITAR is that for the first it does not exist a strategic technology tout-court. A technology may become strategic (or Dual Use) if it exceed specific limits like the one mentioned before. If from the Wassermann point of view it is complex to define such limits (ITAR only recognize the strategic technology) on the other side for the owner (or the end user) of such technology the advantage is that it can be used with the condition to not overcome the established limits.
Radiation Hardening By Design, the main pillar of SkyFlash Project, takes the best from the Wasserman approach because, as a matter of fact, a RHBD component can be completely restricted under the ITAR point of view but from the Wasserman point of view it is restricted only if it exceeds specific limits. This is a quantum leap from the restriction rules point of view.
RHBD, as mentioned in the major part of SkyFlash deliverables and DoW, is a set of techniques and all these methods may be used in a very different way. By applying all annular transistors (NMOS and PMOS), using enhanced guard-rings everywhere and all the techniques described in the literature of SkyFlash it is indeed possible to overtake this value; but it is also possible to relax these rules and provide a device rad-hard enough for the mission (LEO, MEO, GEO) or rad-hard enough to not overtake Wasserman rules. This is a new concept of design based on efficiency, cost and rule observation and SkyFlash consortium is convinced it will be the new approach for future rad-hard component design.
Technology Independence
National and International rules are of course one the obstacles for a real technology independence but other perspectives must be included. A very tailored technology with high complexity where only few players (or only one) can apply changes can represent a restriction exactly like ITAR. In this case two aspects must be evaluated: on one side the technology itself can represent a bottleneck if the complexity inside is to high while on the other the presence of few players (or only one), even if private, may represent an obstacle.
Like persons technologies should be replaceable and like working team, where best characters are chosen more or less the same should be done for enabling technologies.
In the field of semiconductor components there are some assumptions that can be considered. A rad-hard component is usually the result of a silicon process flow (CMOS, SOI, SiGe, etc…) combined with a design flow (circuit design, layout design, firmware and software); the result is a die that must be bonded in a package and finally tested in order to have the green light to be used. Very tailored technologies may be risky because when specific processes are used it is possible that repeat-ability can become an issue. Rad Hard By Process (RHBP) is very keen to obsolescence because of low volume of devices manufactures. Indeed RHBP processes exist (e.g. American Semiconductor) but apart to be ITAR they are also restricted by their small niche of applications. As well known to those skilled in semiconductor manufacturing the higher is the number of manufactured lots the higher is the maturity obtained by the process itself. CMOS 180nm process, the one used in the overall life cycle of SkyFlash Project, represent a well consolidated and mature process. Twenty years ago it was the edge of the technology and now there are much more aggressive process (e.g. 45nm or 22nm) but in these twenty years many wafers by many foundries has been fabricated. Nowadays the yield is in the range of 99,5% and even if this is not an issue for rad-hard components which can of course be much more expensive than a commercial one nevertheless it shows that manufacturing line have the complete control of the process. This is another way to see what a component for space application looks for: repeat-ability; what is manufactured now can be reproduced with almost 100% probability of success. This is Technology Independence.
Since 180nm process is manufactured by many foundries it is also possible to move the design of the component. For sure a technology may be restricted by national rules but it is also possible that the foundry itself change its business or abandon the specific market because not considered strategic. The possibility to move the design from a 180nm platform to another 180nm platform, even if it requires some efforts, is one of the key point for a winning space components. Again, this is Technology Independence.
Manufacturing processes are not forever. This is a basic assumption that Space Community must consider. Nowadays CMOS 180nm is indeed the most suitable for a space component but the Moore Law is (still) running and the technology is moving into the deep submicron era. Silicon foundries are still interested to maintain manufacturing line alive and in good shape but the major part of the income is from consumer market and now this market is not represented by microprocessors, memories and other components sold in billion of parts but it is the market of low level applications such as cheap mobile phones, basic video games or custom applications from small and medium enterprise. Twenty years ago 180nm was terribly expensive and only Intel, AMD, Motorola could afford such technology; now they look at 22nm. But small and medium companies today can use 180nm and indeed they are doing.
This situation will not continue forever. One day also the low level market will move to a more scaled (90nm or less) technology and, consequently, silicon foundries will see also this income to be vanished and in that moment the space niche market will not be enough. This is a threat to Technology Independence.
Saying for how many years 180nm will be available it is rather hard. As a matter of fact there are manufacturing lines still delivering wafers under 250nm so at least other 10 years are reasonable to be expected but the space community must start consider a mid-long term situation with a new process and under these premises there are two options: 90nm or 65nm.
Nowadays CMOS 90nm process is starting to become an old technology (UMC itself is trying to push all its customers towards 65nm) but indeed it has a good level of maturity and this can benefit the space community. On the other hand there is the problem that many foundries has decided to skip this technological node and target directly to the next one represented by 65nm. Under this perspective the risk is to move rad-hard design (including IP cores, VHDL/Verilog codes and rad-hard libraries) to a process that will have a limited success in the low level market. If the low level market will stay on 90nm process (available by a reduced number of silicon foundries if compared to 180nm) for a shorter period the time window for space market can be very narrow forcing to move again to another node (65nm or less).
This is the hard decision to be taken today. CMOS 180nm is reliable for today and tomorrow space products but for the future it is possible that a direct jump to 65nm could be more safe than the one to 90nm.
It is clear that a more scaled technology has some advantages and some disadvantages. In the first one we can mention the resistance in terms of total dose. 90nm and 65nm may rely on thinner oxides and much more clean STI thanks to a more clean deposition removing impurities at the base of holes trapping. For LEO, MEO and GEO it is possible that a very limited number of edgeless transistors can be used with the great advantage to save area in the die. On the other hand the reduced lithography and the reduced junction capacitance at transistor terminals leads to a reduced critical charge in sensitive nodes of the device. Charged particles with lower energy may upset logic ports and memory elements more easily thus leading to increased sensitivity against SEUs, SETs, MBUs and more in general SEFIs. From the hard error perspective also in this case lower energies may be required to trigger a SEL or a SEGR (the last one in particular because of the reduced thickness of oxides) thus leading to enhanced guard rings (waste of area).
RHBD techniques are expected to be adapted in the case of a new technology node. SEE in particular will require on one hand a careful design of circuitry handling with SETs and on the other improved techniques for error correction are expected (with the disadvantage to waste area).
The roadmap defined and pursued in SkyFlash Project had taken into account these premises. Nowadays a 180nm CMOS process has been adopted but in the future a scaled technology is envisaged. Understanding the impact of techniques of radiation hardening by design means to enable and adapt them also in future technologies according to the tradeoff required by resistance against radiation and area consumption. If annular device will probably become the domain for deep space missions only on the other hand enhanced guard ring or new means of shielding will become the main issues for every reliable component (also for LEOs).
In 180nm ECC is not required or it can be lightly used. In more scaled technology ECC will be mandatory to recover the high sensitivity to SEUs in storage elements (SRAMs, Flip-Flops) opening the world of rad-hard on-chip ECCs.
All NVM prototypes developed in SkyFlash have been based on a very radical architectural approach: the use of two memory cells to store a single bit. This is not redundancy nor ECC. A traditional ECC should be based on a 1Mbit array storing data and a second 1Mbit array storing data able to correct the first array (deep Hamming Code) with the inclusion of a digital block intercepting errors and providing corrected bytes. In SkyFlash the bit itself has changed nature and there is no correction: the bit composed by twin cells is more reliable without any correction.
This radical RHBD approach has obviously impacted the overall architecture of the memory. In a conventional ECC approach the single memory block should be the same of a standard memory (same decoders, same sensing scheme, same programming and erasing) but this weakness should be maintained by its intrinsic nature of a device born to work in a standard environment without radiation. On the other hand SkyFlash prototypes have been redesigned from scratch. The physical separation inside the die of the twin cells storing the single bit is a precise decision to avoid that the same ion strike may hit the single bit. The complete removal of reference cells traditionally used in standard NVM has been a precise decision to avoid weak elements which can suffer the degradation from total dose exposure. The decision to use a clock to program and erase a memory and to switch off the same during read mode making the same memory more similar to an asynchronous SRAM is part of a specific RHBD strategy has been done in order to obtain a more safe design against both soft and hard errors.
SkyFlash roadmap has defined not only tricks and methods to avoid or mitigate radiation effects but also new means of architecture and floor-planning. Several general assumption on how to realize a rad-hard device are indeed typical of memory design but they can easily moved to a more general mixed signal IC. Moreover all these assumption are independent from the technology node. In SkyFlash it has been on CMOS 180nm but the same approach and the general vision may be moved to 90nm or 65nm. Again, this is Technology Independence.
During the final meeting on February 28th 2014 and in deliverable D.1.7 has been reported a slide shown hereinafter summarizing the obtained achievements and defining future perspectives.
SkyFlash has represented an effort to a roadmap showing how a rad-hard memory can move through several available technologies. Today it is CMOS 180nm process with charge trap memory cells based on nitride but tomorrow it can be a more scaled technology (90nm or 65nm) with different memory cells (RRAM, PCM, MTJ). The strong methodological approach followed by SkyFlash has pursued the main pillar of Technology Independence such as strongly asked by the European Union and the European Space Agency.
Conclusion
SkyFlash Project has been concluded on time according to roadmap defined in the DoW. These 30 months has taken the knowledge of the Consortium in the field of NVM to a new level of awareness and many lessons have been learnt.
SkyFlash has been and will be a relevant platform for future endeavors in the same field by using new technologies and manufacturing process.
List of Websites:
http://www.skyflash.eu/
Dr. Cristiano Calligaro, RedCat Devices srl, via Valsolda 21, 20142 MILANO (ITALY)