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Universal Message-Passing Architectures

Objective

The objective of PUMA is to develop a family of transputer-based components providing low-latency global communications, and to investigate networking and software techniques for the exploitation of parallel processing machines having a greatly increased capability for non-local communications.
The hardware to be developed within the project includes the communications mechanism of the new H1 transputer, a routing/switch chip to enable the H1 to be fully exploited in multi-transputer systems, and chips to perform link interfacing (between existing transputers and H1) and link adaptation.
New parallel computer architectures based on low-latency, global communications require improved techniques in network communication theory, compilers and language design. These issues are being addressed within the project. Performance improvements through automatic placement and migration of processes are also being studied. The project aims to provide the new concepts rather than to develop fully engineered compilers and operating systems etc. Research will also be carried out into the more speculativePRAM model of parallel computation.
PUMA is complementary to the GENESIS projects (numbers 2427 and 2702), and has links with SUPERNODEII (2528).
Performance evaluation results and ensuing recommendations for the design and architecture of future transputer based networks for scalable, universal message passing machines have been collected. The main method used for the investigations was the simulation of network and load models on the packet level, partly extended by a novel combination with analytical models. 3 important steps of performance evaluation and their results have been evaluated. In the first step, sustained random communication performance is evaluated with respect to the predicition of throughput and delay, their variation with the network size and cost relative comparison of the different topologies. In the second step, various routing schemes are investigated for their performance effects on different load patterns. Finally, the effects of hot spot load and of network partitioning have been investigated.

The objective of the project was to develop a family of transputer based components providing low latency global communications, and to investigate networking and software techniques for the exploitation of parallel processing machines having a greatly increased capability for nonlocal communications.
The hardware developed within the project includes the communications mechanism of the new H1 transputer (the T900), a routing/switch chip to enable the H1 to be fully exploited in multitransputer systems, and chips to perform link interfacing (between exisitng transputers and H1) and link adaption.
New parallel computer architectures based on low latency, global communications require improved techniques in network communication theory, compilers and language design. These issues are bein addressed within the project. Performance improvements through automatic placement and migration of processes are also being studied. The project aims to provide the new concepts rather than to develop fully engineered compilers and operating systems etc. Research will also be carred out into the more speculative PRAM model of parallel computation.
Work on transputer components for communications (C100, C104) has progressed well. Results from network simulations have influenced the C104 for the internal registers and the adaptive routing mechanism. The virtual channel router (VCR), by simulating the system's communications, has aided the study of software development. The evaluation of new concepts has been made using applications for physical and mathematical libraries.
The H1 has been announced by INMOS as the T9000.
Work on transputer components for communications (C100, C104) has progressed well. Results from network simulations have influenced the C104 for the internal registers and the adaptive routing mechanism. The VCR (virtual channel router), by simulating thesystem's communications, has aided the study of software development. The evaluation of new concepts has been made using applications for physical and mathematical libraries.
Exploitation
The project has made significant advances towards general purpose, scalable parallel computation techniques and should form a strong and timely foundation on which to base the development of the next generation of parallel computing machines. Arising fromwork in the project, commercial software is now available for computer-aided design and verification of silicon devices. The VCR system is also available on a commercial basis.

Coordinator

Inmos Ltd
Address
1,000 Aztec West
BS12 4SQ Almondsbury
United Kingdom

Participants (12)

Bull SA
France
Address
Tour Bull 1 Place Carpeaux Puteaux
92039 Paris La Défense
Chorus Systèmes SA
France
Address
6 Avenue Gustave Eiffel
78182 Saint-quentin-en-yvelines
Defence Research Agency (DRA)
United Kingdom
Address
St Andrews Road
WR14 3PS Malvern
Gesellschaft für Mathematik und Datenverarbeitung mbH
Germany
Address
Schloß Birlinghoven
53754 Sankt Augustin
SIEMENS AG
Germany
Address
Otto-hahn-ring 6
81739 München
Syseca SA
France
Address
4 Square René Cassin
35100 Rennes
Technische Universitaet Muenchen
Germany
Address
Arcisstrasse 21
80333 Muenchen
UNIVERSITY OF SOUTHAMPTON
United Kingdom
Address
Southampton Ocenagraphic Centre, European Way
SO14 3ZH Southampton
University of Liverpool
United Kingdom
Address
Brownlow Hill
L69 3BX Liverpool
University of Oxford
United Kingdom
Address
11 Keble Road
OX1 3QD Oxford
Warwick Strategic Technologies
United Kingdom
Address
Barclays Venture Centre Warwick Science Park
CV4 7EZ Coventry
École Nationale Supérieure des Mines de Paris
France
Address
35 Rue Saint-honoré
77305 Fontainebleau