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Performances and Physical Limits of Heterostructure Field-Effect (HEFT) Transistors

Objective

The current trend in microelectronics points towards a further scaling-down of semiconductor devices to nanometre-scale dimensions. This trend is driving the continuing development of micro- and nanofabrication techniques. However, understanding is lacking of electron-transport phenomena in these very small device structures.
The aim of the NANOFET Action was to undertake a systematic investigation of the behaviour of nanometre-scale field-effect transistors. The GaAs-based HFET has been selected for investigation because parasitic phenomena affecting electron transport are minimised in this device. The results expected from this Action will be a major step towards understanding the relationships between the observed device characteristics and the underlying physical phenomena which determine electron transport.
The performance and physical limits of heterostructure field effect (HFET) transistors scaled down to ultrasubmicron dimensions were studied. The main focus is on horizontal electron transport in nanometre scale field effect transistors. The new technologies and methodologies needed to simulate, fabricate and characterize these very small devices were also developed. The results should allow guidelines to be drawn up for the next gneration of HFETs for information technology applications.

The main results of the research have been the following:
fabrication of high performance HFET transistors with gatelength below 0.1 micron and submicron source drain distance;
extensive simulation (1-dimensional and 2-dimensional) of nanometre scale HFETs, using Monte-Carlo and hydrodynamic models;
development of advanced microwave characterization models and techniques for HFETs, both at ambient and at cryogenic temperatures;
development of models and techniques for electrooptic sampling of electron transit times in HFET devices.
APPROACH AND METHODS
-Epitaxial layers. Both AlGaAs/GaAs and strained AlGaAs/InGaAs layers were grown on GaAs by molecular beam epitaxy (MBE). Various layer structures were compared and the vertical dimensions optimised with respect to the horizontal scale of the device. -Device processing. The smallest devices have a nanometre gate-length and a submicron source-drain gap. To fabricate the gate, e-beam-based nanolithography was being used. The fabrication of source, drain and channel regions involves both standard and ad vanced processing steps such as dry-etched gate recess and epitaxial ohmic contacts.
-Device simulation. Monte Carlo techniques were used to investigate electron transport in very small two-dimensional structures.
-Electrical characterisation. Complete HF characterisation was performed on-wafer, using the proper de-embedding techniques. Small-signal parametric models are under development.
-Electro-optic sampling. In order to study transient transport in very small devices, electro-optic sampling techniques were developed with femtosecond laser excitations.
PROGRESS AND RESULTS
The main results of the Action have been the following:
-fabrication of high performane HFET transistors with gatelength below 0.1 micron and submicron source-drain distance
-extensive simulation (1D and 2D) of nanometer scale HFET's, using Monte-Carlo and hydrodynamic models
-development of advanced microwave characterization models and techniques for HFET's, both at ambient and at cryogenic temperatures
-development of models and techniques for electro-optic sampling of electron transit times in HFET devices
POTENTIAL
Although the major aim of the consortium is still to obtain fundamental physical information on very small HFET's, the industrial implications of this work have become increasingly clear during the second year. The combination of simulation, processing and characterisation techniques developed in this project has resulted in "classical" devices with record performances. In order to further exploit these results, links have been established with the ESPRIT GIANTS consortium which is carrying out applications-oriented work on submicron HFETs. Collaborative actions between the two Actions have been planned on selected topics.

Coordinator

Interuniversitair Mikroelektronica Centrum
Address
Kapeldreef 75
3030 Heverlee
Belgium

Participants (4)

Association pour la Recherche et le Développement de Méthodes et Processus Industriels (ARMINES)
France
Address
60 Boulevard Saint-michel
75272 Paris
Centre National de la Recherche Scientifique (CNRS)
France
Address
Université De Paris Xi (Université Paris-sud)
91405 Orsay
Centre National de la Recherche Scientifique (CNRS)
France
Address
1919 Route De Mende
34405 Montpellier
University of Cambridge
United Kingdom
Address
Trumpington Street
CB2 1PZ Cambridge