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Content archived on 2024-04-16

Power and Timing Modelling for Optimisation and Specification


This Action aims to develop a method of modelling, optimising and specifying the power and timing of very high-speed integrated circuits (VHSICs) using technologies such as GaAs, CMOS, BiCMOS, SOS, SOI and ECL. An experimental implementation will apply methods of performance and power modelling for VHSICs to optimising complex digital system designs. The new approach should work for conservative technologies as well.
A new method to cope with the design of very complex and high speed circuits and systems is being developed. This method will enable system designers who are not specialists at near-silicon levels to implement high-performance circuits. The method will be implemented in an experimental system and applied to selected circuit design examples. The action has concentrated on the following aspects:

power estimation of regular structures;
statistical power estimation (synchronised event power model);
timing modelling by abstraction;
characterization of interconnect;
characterization of cells;
circuit extraction of parameters in multiconductor transmission lines.
The first tasks are to define:
-methods for modelling interconnects and devices in the power and timing domain
-a notation for the adaptation of the methods adopted to different technologies
-a method to extract all data needed from the layout.
Methods will then be developed for implementation in an experimental system that will be validated and evaluated with respect to selected GaAs and CMOS circuit design examples.
The action has concentrated on the following aspects:
-power estimation of regular structures
-statistical power estimation (synchronised event power model)
-timing modelling by abstraction
-characterisation of interconnect
-characterisation of cells
-circuit extraction supporting interconnect modelling
-accurate extraction of parameters in multiconductor transmission lines
The results of the Action will form the basis of a design for performance methods for complex VHSICs adaptable to a wide variety of technologies. The effect of the method being developed will be a substantial reduction in the frequency of reimplementationof an important class of CAE tools.


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Erwin Schroedinger Strasse 46

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