Objective
The research underway in the ASCIS Action is vital to the design of future ICs, which will contain the equivalent in logic of 16 million memory cells. Current design systems support mainly structural synthesis from the architectural down to the layout level. To fully exploit the integration complexity of future fabrication technologies, it is crucially necessary to provide a specification at the highest system level and to exploit (interactive) high-level synthesis techniques to arrive at an efficient ASIC architecture. The Action's objective is "true" silicon compilation, which allows several mapping strategies and architectural approaches and can handle a broad class of applications. The ultimate goal is to pave a complete path from specification to architecture. e.
System-level specification techniques and high-level synthesis techniques for the efficient design of application-specific integrated circuit (ASIC) architectures were developed. Currently, complex systems are mapped with the help of computer-aided design (CAD) tools onto silicon, starting from a register-transfer (RT) level architectural description. However, the bottleneck in mega-chip designs does not lie in realising the layout from this RT level description, but in mapping the intended behaviour onto a suitable architecture. Work has focused on investigating novel design methodologies. These are tested (partly manually, partly with prototype design tools) on realistic examples derived from real-life applications. The main results include the following. Firstly, a new abstract system model based on Petri nets, defined and evaluated on several algorithms, and a successful implementation of formal verification with propositional temporal logic. Secondly, new contributions to methodologies for mapping algorithms described at a high level onto regular array architectures, (in particular direct mapping of nested loops and re-indexing of descriptions) and onto multiplexed datapath architectures with complex controllers (in particular in the areas of datapath definition, scheduling and assignment). Thirdly, the development of general global optimization techniques based on neural nets and genetic algorithms, and finally, for controller synthesis, optimizations at both the architecture and timing levels.
APPROACH AND METHODS
Research at different levels on the design trajectory from system description to architecture is being pursued, namely:
-system definition in terms of formal specification of abstract behaviour and formal verification of correctness
-system partitioning
-mapping of subsystems onto architectures with the development of synthesis strategies for regular arrays and lowly multiplexed data-paths (where the main emphasis of the project lies)
-investigation of new optimisation paradigms for use in synthesis systems (examples are genetic algorithms and neural nets)
-architectural synthesis for the control part with design optimisation and technology mapping techniques.
The shortcomings of each level are being identified and ways of tackling them defined. Efficiency of the resulting architectures (in terms of throughput, chip-area and memory) is an important objective. The resulting IC designs will comply with the band-width, power and pin-count limitations of VLSI components.
PROGRESS AND RESULTS
Work has focused on investigating novel design methodologies. These are tested (partly manually, partly with prototype design tools) on realistic examples derived from real-life applications. The main results so far are:
-A new abstract system model based on Petri-nets, defined and evaluated on several algorithms, and a successful implementation of formal verification with propositional temporal logic.
-New contributions to methodologies for mapping algorithms described at a high level onto regular array architectures, in particular direct mapping of nested loops and re-indexing of descriptions, and onto multiplexed datapath architectures with complexcontrollers, in particular in the areas of datapath definition, scheduling and assignment.
-General global optimisation techniques based on neural nets and genetic algorithms.
-For controller synthesis, optimisations at both the architecture and timing levels. Formal verification of layout vs. behavioural specification by means of novel extraction techniques.
POTENTIAL
The results stemming from the ASCIS Action are of crucial importance for future designs in many application domains, such as image-processing, telecommunication and factory automation. For complex systems such as these, at least 70% of the design effort is currently spent on arriving at the architectural specification. The ASCIS action helps to bypass this severe bottleneck by automating the synthesis process leading from behaviour to architecture. A transfer of these new technologies to development-oriented projects (with the participation of large systems companies) will help shape the future ASIC and systems industry in Europe in the second half of the decade.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
- agricultural sciences agricultural biotechnology
- social sciences sociology industrial relations automation
- natural sciences chemical sciences inorganic chemistry metalloids
- natural sciences computer and information sciences software software applications simulation software
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Coordinator
3030 HEVERLEE
Belgium
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