Multi - Functional Integrated arrays of Interferometric switched

Project Information

MUFINS

Grant agreement ID: 4222

Project closed

Start date 1 September 2004

End date 31 August 2007

Funded under

• Information Society Technologies: thematic priority under the specific programme "Integrating and strengthening the European research area" (2002-2006).

Total cost € 3 530 232,00

EU contribution € 2 694 795,00

Coordinated by

RESEARCH ACADEMIC COMPUTER TECHNOLOGY INSTITUTE
Greece

Exploitable results

Optical switches

The MUFINS project aims to develop arrays of generic optical switches integrated on a single chip, and to prove their multi-functional nature by using them to implement token all-optical circuits. The integration of arrays of generic switches will significantly reduce the cost per switch, and will initiate efforts for production of optical switches on a single chip, similarly to the early years of the electronic VLSI. WP2 main objectives were to define the operational parameters for the components and sub-systems used in the MUFINS platform (multi-element arrays), to develop two single, hybrid MZI switches, to demonstrate an Exchange Bypass operation at 10 Gb/s by using one of the developed MZI switches, to demonstrate a Clock and Data Recovery circuit at 10 Gb/s by using both the developed MZI switches and to perform simulation studies in order to evaluate the cascadability capabilities of the switches. Following these objectives, the initial specifications of the 2x2 switch array devices have been defined. In particular the approach that would be used for the development of these devices and, more specifically, the key features required for the active components, in order to make them compatible with the hybrid platform, has been identified. The most important aspects for the MUFINS devices development have been identified to be flip-chip mounting, precision cleaving, mode expansion and the definition of the vertical alignment layer. The objectives of WP3 were to design and fabricate 2- and 4-element, 10 Gb/s MUFINS monolithically integrated devices by using active/passive regrowth (TU/e) and active vertical coupling (UNIVBRIS) integration technologies, to design and fabricate three (3) hybridly integrated, 4-element, 40 Gb/s MUFINS devices (CIP) and to evaluate the developed devices by using them to demonstrate a header extraction, a half-adder, a full adder and a time slot interchanger (TSI) circuit, all at 10 Gb/s. RACTI has experimentally evaluated one of the hybrid quad arrays developed by CIP, by demonstrating header extraction, and clock and data recovery circuits at 40 Gb/s. Although the clock and data recovery was originally planned to be implemented in WP3 and at 10 Gb/s, and the header extraction to be implemented in WP4 at 40 Gb/s (in a later stage of the project), these experiments have been combined and demonstrated simultaneously at 40 Gb/s (Figure 11), by using the hybridly integrated quad MZI array delivered by CIP. RACTI has also successfully demonstrated the Time Slot Interchanger circuit at 10 Gb/s, by using all the four (4) MZI switches of one of the hybrid quad arrays, developed by CIP within WP3. The 4 MZI switches of the integrated array were serially connected and error-free operation was achieved with power penalties of 0.2 dB, 0.78 dB, 1.43 dB and 1.8 dB after the first, second, third and fourth MZIs, with respect to the input signal. The error-free operation of the proposed TSI architecture shows the cascadability of the SOA-MZI switches comprising the quadruple array in complex multi-gate schemes and their potential to function properly even with more than one wavelength appearing simultaneously at their input. The objectives of WP4 were to develop monolithic, 2-element and 4-element (MZIs) MUFINS platforms, operating at 40 Gb/s, by incorporating active/passive integration (TU/e), and active vertical coupling (UNIVBRIS). On the evaluation side, the objectives of WP4 were to demonstrate a Clock and Data Recovery, a Data Vortex switch, and a 4x4 Optical Switching Matrix, all at 40 Gb/s. TU/e successfully realised the 40 Gb/s 4-element MUFINS switches, which have been packaged and pigtailed by CIP (Figure 16). Initial characterization proved successful switching at 40 Gb/s. The polarization converters and splitters for the POLARIS concept have also been realized by TU/e. This also involved new processing development, to allow integration of these devices with the MUFINS switches. The splitters and converters showed acceptable performance. The full integrated circuit has also been realized. The objectives of WP5 were to use the developed integrated MZI arrays, so as to assemble a 4-wavelength Burst Mode Receiver circuit, to test it using a single wavelength and finally, to evaluate it using four (4) wavelengths simultaneously at 10 Gb/s.