The aim of this project was to significantly increase the ESD hardness of CMOS technologies in the submicron range by improving the understanding of ESD phenomena and developing technology-independent guidelines based on a detailed investigation of relevant parameters and realistic stress models.
The aim of this project is to significantly increase the electrostatic discharge (ESD) hardness of complementary metal oxide semiconductor (CMOS) technologies in the submicron range by improving the understanding of ESD phenomena and developing technology independent guidelines based on a detailed investigation of relevant parameters and realistic stress models.
Several types of ESD testers and stress models (human body, charged device and machine models), used to determine the ESD hardness of integrated circuits, are being characterised, and are being shown to give nonconformal results, even within the limits of the existing military (MIL) standards. The results will be further correlated with field returns. A proposal for the standardisation of ESD stress models and related procedures is being set up and is under discussion in the standardization group for ESD testing. Several new types of ESD testers related to charged device model testing are being compared with the prototype built in this project.
Failure criteria characterizing the effectiveness of ESD protection measures with respect to fatal and latent damage are being defined. Besides bulk CMOS, particular attention is being paid to problems specific to silicon-on-insulator (SOI) technologies, where energy dissipation is considerably hampered by the isolated structure, and conventional protectioncircuits cannot be used adequately. Layout variations of devices, different types of devices, protection circuits with varied device combinations, and protected circuits are being investigated with respect to the different failure criteria. Adequate monitor circuits have been developed. An initial set of guidelines for improving the ESD hardness for processes and circuits its being generated. The influence of different packages on failure mechanisms and thresholds will also be considered. Complex electrothermal simulation tools, capable of handling the ESD-relevant voltage and current ranges as well as time and fr equency domains, will be developed. They will be verified and improved using the experimental results and failure analysis data available from the 2 previous workpackages, and will provide the basis for designing tailor made protection solutions for future generations of integrated circuits (IC).
Submicron CMOS technologies show increased sensitivity to electrostatic discharge (ESD) due to reduced gate oxide thickness, shallow junctions, lightly doped drain and lack of high resistive interconnections, which tend to reduce circuit reliability. On the other hand, the need for high pin counts, high signal frequencies and advanced analogue performance puts even higher demands on reliability. As a consequence, a special tailor-made protection strategy preventing the inner logic from being damaged by ESD voltages and currents must be found for each application so as to reconcile these opposing trends. Because of the complexity of the problem, reliable guidelines for the optimised design of future protection systems are needed, but are not yet available.
Funding Schemeundefined - undefined
5656 AA Eindhoven