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Proving and Testability for Reliability Improvement of Complex Integrated Architectures


The project aims to provide a set of architectural-level design methodologies and prototype design support tools. These will allow a designer to prove formally the correctness of a design, evaluate its testability at a high level of abstraction, and assess its complexity in terms of its silicon implementation. These tools will operate at a very high level of abstraction, allowing a designer to make reasoned decisions about architectural choices. The new tools, rather than constituting an architecture compiler, will consist of a set of advisers that provide information on such design issues as correctness, testability, and complexity.
The project aims to provide a set of architectural level design methodologies and prototype design support tools. This project will also investigate the feasibility of building computer aided design (CAD) tools based on a set of high level advisers.
There have been 2 major lines of workon formal methods. The first focuses on developing algebraic representations of specifications and components and techniques for reasoning about them. The second line of work has been based on Abstract Hardware's LAMBDA/DIALOG verification tools, and has involved training the other industrial partners in their use and collaborative working on some actual industrial problems in order to devbleop the tools and their interfaces.
Prototype software has been developed to perform test pattern generation for 1-dimensional and 2-dimensional regular arrays, binary tree architectures and some commonly used very large scale integration (VLSI) circuit blocks (adder, decoder, shifter) from a graph description. Algorithms have been developed for testability analysis of array architectures and the graphical analysis of arrays at a variety of levels of abstraction has been investigated. A knowledge acquisition process for collecting and formalizing testability rules has been undertaken together with a study of available expert system shells prior to the construction of a testability adviser. Fault mapping rules for systolic and semisystolic arrays of different interconnection topologies have been formalized. A representation at the functional level has been defined for sequential machines and associated faults, together wilth a test procedure allowing full functional fault coverage to be obtained. Prototype software has been developed, including the definition of abstract data structures, to describe systems under test. The insertion of testability rules for regular structures into the selected expert system shell has been completed. A C environment for the evaluation of the conditions associated w ith these rules has been partially developed. A taxonomy of design for testability techniques has been started and a literature survey and interviews undertaken to extract the rules used in current design flow. This information will be formalized for inclusion in the testability adviser.
Activity on complexity analysis has focused on the formal definition of data flow graph models (both general and iterative) and on the analysis and manipulation of these models for the synthesis of alternative architectures. The analysis of architectural and technological requirements derived from diode function generator (DFG) models has commenced in order to verify design feasibility. Considerable care has been taken to ensure that the project utilizes a unified graph representation across the above 3 strands of work.
Moreover, such advisers can be technology-independent, permitting a final design to be implemented in various microelectronics technologies, depending upon further considerations (second sourcing, etc.) that do not strictly relate to architecture design constraints. Thus designs can be optimised at high-level prior to choosing a specific microelectronics technology for its implementation.

The project will provide:

- Further development of formal proving methods to meet the demands of high-complexity architecture design.
- Formal proving methods at the logical level, and a problem reformulation system to move up and down levels.
- Methods for evaluating the testability of complex digital architectures, starting from a high-level representation.
- Techniques for generation and evaluation at high level of alternative architectures.


Brunel University
Howell Building
UB8 3PH Uxbridge
United Kingdom

Participants (4)

United Kingdom
Kingston Lane
GEC Avionics
United Kingdom
Airport Works
ME1 2XX Rochester
Italtel Società Italiana Telecomunicazioni SpA
Castelletto Di Settimo Milanese
20019 Milano
Politecnico di Milano
Piazza Leonardo Da Vinci 32
20133 Milano